FIG. 15A is a plan view illustrating a semiconductor device according to a third exemplary embodiment in accordance with principles of inventive concepts. FIGS. 15B, 15C, 15D, and 15E are cross-sectional views taken along lines I-I′, II-II′, III-III′, and IV-IV′ of FIG. 15A, respectively. FIG. 15F is a cross-sectional view corresponding to the line IV-IV′ of FIG. 15A to illustrate a semiconductor device according to a modified embodiment of a third exemplary embodiment in accordance with principles of inventive concepts. In the present exemplary embodiment, the same elements as described in the first embodiment of FIGS. 1A to 1C will be indicated by the same reference numerals or the same reference designators. For the purpose of ease and convenience in explanation, descriptions of the same elements as in the first embodiment will be omitted or only briefly described.
Referring to FIGS. 15A, 15B, 15C, 15D, and 15E, a device isolation layer ST defining a plurality of active patterns AP1, AP2, and AP3 may be provided on a substrate 100. The active patterns AP1, AP2, and AP3 may include a first active pattern AP1, a second active pattern AP2, and a third active pattern AP3 that are spaced apart from each other with the device isolation layer ST interposed therebetween. Each of the active patterns AP1, AP2, and AP3 may have a bar shape extending in a first direction D1. The active patterns AP1, AP2, and AP3 may be spaced apart from each other in a second direction D2 intersecting the first direction D1.
