The gate electrodes GE may be provided on the active patterns AP1, AP2, and AP3 and may extend in the second direction D2. According to an exemplary embodiment, the gate electrodes GE may cover top surfaces of the active patterns AP1, AP2, and AP3 and a top surface of the device isolation layer ST, as illustrated in FIG. 15E. According to another exemplary embodiment, each of the gate electrodes GE may cover the top surface and the exposed sidewalls of each of the active patterns AP1, AP2, and AP3 and may extend onto the top surface of the device isolation layer ST, as illustrated in FIG. 15F. A gate insulating pattern GI may be provided between each of the gate electrodes GE and each of the active patterns AP1, AP2, and AP3. The gate insulating pattern GI may extend along a bottom surface of each of the gate electrodes GE in the second direction D2. A capping pattern CAP may be provided, or formed, on a top surface of each of the gate electrodes GE, and gate spacers GS may be provided on both sidewalls of each of the gate electrodes GE. Source/drain regions 110 may be provided in the active patterns AP1, AP2, and AP3 at both sides of each of the gate electrodes GE. As a result, a first transistor TR1, a second transistor TR2, and a third transistor TR3 may be realized, or implemented, on the substrate 100. The first transistor TR1 may include the first active pattern AP1, and the second transistor TR2 may include the second active pattern AP2. The third transistor TR3 may include the third active pattern AP3.
