Referring again to FIGS. 15A to 15E, gate electrodes GE may be formed to intersect active patterns AP1, AP2, and AP3. The gate electrodes GE may be provided on the active patterns AP1, AP2, and AP3 and may extend in the second direction D2. In an exemplary embodiment, the gate electrodes GE may cover the top surfaces of the active patterns AP1, AP2, and AP3 and the top surface of the device isolation layer ST, as illustrated in FIG. 15E. In another exemplary embodiment, each of the gate electrodes GE may cover the top surface and the exposed sidewalls of each of the active patterns AP1, AP2, and AP3 and may extend onto the top surface of the device isolation layer ST, as illustrated in FIG. 15F. A gate insulating pattern GI may be formed between each of the gate electrodes GE and each of the active patterns AP1, AP2, and AP3. A capping pattern CAP may be formed on a top surface of each of the gate electrodes GE, and gate spacers GS may be formed on both sidewalls of each of the gate electrodes GE. The gate insulating pattern GI, the gate electrodes GE, the capping patterns CAP, and the gate spacers GS may be formed by the substantially same method as described in the first embodiment with reference to FIGS. 1A to 1C. Thereafter, source/drain regions 110 may be formed in each of the active patterns AP1, AP2, and AP3 at both sides of each of the gate electrodes GE.
