In accordance with another aspect of the present disclosure, a semiconductor device includes a first potential supply line for supplying a first potential, a second potential supply line for supplying a second potential lower than the first potential, a functional circuit, and at least one of a first switch disposed between the first potential supply line and the functional circuit and a second switch disposed between the second potential supply line and the functional circuit. The first switch includes a first MOS FET and a first negative capacitor showing a negative capacitance and having a first terminal and a second terminal, and the first terminal of the first MOS FET is electrically coupled to a gate of the first MOS FET. The first terminal of the first negative capacitor is a first gate electrode of the first MOS FET. The second switch includes a second MOS FET and a second negative capacitor showing a negative capacitance and having a first terminal and a second terminal, and the first terminal of the second MOS FET is electrically coupled to a gate of the second MOS FET. The second terminal of the second negative capacitor is a second gate electrode of the second MOS FET. In one or more of the foregoing and/or following embodiments, the semiconductor device includes both the first switch and the second switch. In one or more of the foregoing and/or following embodiments, the functional circuit includes an internal potential supply line to which sources of a plurality of MOS FETs of the functional circuit are coupled, and a drain of the MOS FET of the switch is coupled to the internal potential supply line and a source of the MOS FET of the switch is coupled to the first potential supply line. In one or more of the foregoing and/or following embodiments, the functional circuit includes a plurality of MOS FETs, and at least one of the plurality of MOS FETs of the functional circuit has a same gate length as at least one of the first MOS FET and the second MOS FET. In one or more of the foregoing and/or following embodiments, the functional circuit includes a plurality of MOS FETs, and at least one of the plurality of MOS FETs of the functional circuit has a same gate dielectric layer thickness as at least one of the first MOS FET and the second MOS FET. In one or more of the foregoing and/or following embodiments, the functional circuit includes a plurality of fin field effect transistors (FinFETs), and the first MOS FET and the second MOS FET are FinFETs.