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Semiconductor device including standard cells with header/footer switch including negative capacitance

專(zhuān)利號(hào)
US10868132B2
公開(kāi)日期
2020-12-15
申請(qǐng)人
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.(TW Hsinchu)
發(fā)明人
Chien-Hsing Lee; Chih-Sheng Chang; Wilman Tsai; Chia-Wen Chang; Ling-Yen Yeh; Carlos H. Diaz
IPC分類(lèi)
H01L29/51; H01L29/66; H01L27/11; H01L27/092; H01L29/16; H01L29/40; H01L29/78
技術(shù)領(lǐng)域
fet,mos,nc,gate,dielectric,layer,fets,potential,switch,in
地域: Hsinchu

摘要

A semiconductor device includes a first potential supply line for supplying a first potential, a second potential supply line for supplying a second potential lower than the first potential, a functional circuit, and at least one of a first switch disposed between the first potential supply line and the functional circuit and a second switch disposed between the second potential supply line and the functional circuit. The first switch and the second switch are negative capacitance FET.

說(shuō)明書(shū)

For the MOS FET portion, the sub-threshold swing is expressed by equation (3), where VG is the applied gate bias, Ψs is the surface potential, Cs is the semiconductor capacitance, and Cins is equal to the gate insulator capacitance Cox. The “1+Cs/Cins” is larger than 1, and therefore the limit Swing dictated by Boltzmann distribution is about 60 mV/dec at room temperature.

Swing = ? V G ? ( log 10 ? ? I ) = ? V G ? ψ s ? ? ψ

權(quán)利要求

1
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