Source and drain surface treatment for multi-gate field effect transistors
地域：
Hsin-Chu
摘要
A method includes providing a structure having a substrate and a fin extending from the substrate, wherein the fin includes a first semiconductor material and has a source region, a channel region, and a drain region for a transistor; forming a gate stack over the channel region; performing a surface treatment to the fin in the source and drain regions, thereby converting an outer portion of the fin in the source and drain regions into a different material other than the first semiconductor material; etching the converted outer portion of the fin in the source and drain regions, thereby reducing a width of the fin in the source and drain regions; and depositing an epitaxial layer over the fin in the source and drain regions.
說明書
This application is a divisional application of U.S. patent application Ser. No. 15/964,398, filed on Apr. 27, 2018, which claims priority to U.S. Provisional Patent Application Ser. No. 62/593,001 filed on Nov. 30, 2017, each of which is incorporated herein by reference in its entirety.
The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
權(quán)利要求
What is claimed is:1. A device comprising:a semiconductor fin structure disposed over a substrate, the semiconductor fin structure having a channel region and a source/drain region, the channel region having a first width and the source/drain region having a second width that is less than the first width; a shallow trench isolation structure disposed on the substrate proximate the semiconductor fin structure, the shallow trench isolation structure having a sidewall facing the semiconductor fin structure; and a liner layer extending from the sidewall of the shallow trench isolation structure to a sidewall of the semiconductor fin structure. 2. The device of claim 1 , further comprising:a gate structure disposed over the channel region of the semiconductor fin structure; a source/drain feature disposed over the source/drain region of the semiconductor fin structure. 3. The device of claim 2 , wherein the source/drain feature extends into and physically contacts the channel region of the semiconductor fin structure. 4. The device of claim 3 , wherein the source/drain feature includes an epitaxial material, andwherein the epitaxial material physically contacts the channel region of the semiconductor fin structure. 5. The device of claim 1 , wherein the channel region of the semiconductor fin structure has a first height and the source/drain region of the semiconductor fin structure has a second height that is less than the first height. 6. The device of claim 1 , wherein the source/drain region of the semiconductor fin structure has an upper portion, a middle portion and a lower portion, wherein the middle portion is disposed between the upper and lower portions, and wherein the upper portion is wider than the middle portion and the lower portion is wider than the middle portion. 7. The device of claim 1 , wherein the liner layer has a top surface facing away from the substrate and the shallow trench isolation structure has a top surface facing away from the substrate, wherein the top surface of the liner layer extends to a first height and the top surface of the shallow trench isolation structure extends to a second height that is greater than the first height. 8. A device comprising:a semiconductor fin structure disposed over a substrate, the semiconductor fin structure having a channel region and a source/drain region, the source/drain region of the semiconductor fin structure including:a first portion having a first width; a second portion disposed over the first portion, the second portion having a second width that is different than the first width; and a third portion disposed over the second portion, the third portion having a third width that is different than the second width, wherein the channel region of the semiconductor fin structure has a fourth width that is greater than the first, second and third widths; a gate structure disposed over the channel region of the semiconductor fin structure; and a source/drain feature disposed over the source/drain region of the semiconductor fin structure, wherein the source/drain feature extends under a portion of the gate structure and into the channel region of the semiconductor fin structure such that the source/drain feature physically contacts the channel region of the semiconductor fin structure. 9. The device of claim 8 , wherein the gate structure includes a sidewall spacer and the source/drain feature extends under a portion of the sidewall spacer and into the channel region of the semiconductor fin structure. 10. The device of claim 8 , wherein the second portion and the third portion of the source/drain region of the semiconductor fin structure are formed of the same material, andwherein the first portion of the source/drain region of the semiconductor fin structure is formed of a different material than the second portion and the third portion of the source/drain region of the semiconductor fin structure. 11. The device of claim 8 , further comprising:a dielectric isolation structure disposed on the substrate proximate the semiconductor fin structure; and a liner layer extending from the shallow trench isolation structure to a sidewall of the semiconductor fin structure. 12. The device of claim 11 , wherein the liner layer has a top surface facing away from the substrate and the dielectric isolation structure has a top surface facing away from the substrate, wherein the top surface of the liner layer extends to a first height and the top surface of the shallow trench isolation structure extends to a second height that is greater than the first height. 13. The device of claim 11 , wherein the liner layer has a top surface facing away from the substrate and the dielectric isolation structure has a top surface facing away from the substrate, wherein the top surface of the liner layer extends to a first height and the top surface of the shallow trench isolation structure extends to a second height that is less than the first height. 14. The device of claim 8 , wherein the channel region of the semiconductor fin structure has a first height and the source/drain region of the semiconductor fin structure has a second height that is less than the first height. 15. A device comprising:a dielectric isolation layer disposed on a substrate; a fin extending from the substrate and through the dielectric isolation layer, the fin including a first semiconductor material, the fin having a source/drain (S/D) region and a channel region, wherein a width of the S/D region is smaller than a width of the channel region; an epitaxial layer covering the S/D region; and a dielectric liner surrounding a bottom portion of the fin, wherein the dielectric liner has a lower portion below a top surface of the dielectric isolation layer and an upper portion above the top surface of the dielectric isolation layer. 16. The device of claim 15 , wherein a height of the S/D region is smaller than a height of the channel region. 17. The device of claim 15 , wherein a portion of the epitaxial layer extends into the channel region. 18. The device of claim 15 , wherein the first semiconductor material includes silicon germanium. 19. The device of claim 15 , wherein the fin further includes a second semiconductor material that is different than the first semiconductor material. 20. The device of claim 15 , wherein the dielectric liner includes a dopant such that that the dielectric line is a doped dielectric liner.
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