Referring to FIG. 9, in a first step, a contact etch stop (CES) layer 134 is formed to cover the device 100. In the illustrated embodiment, the CES layer 134 is deposited as a blanket layer over the gate stack 120, sidewalls of the gate spacer 122, the source/drain features 130, and over the top surface of the isolation structure 112. The CES layer 134 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, other dielectric materials, or combination thereof. The CES layer 134 may be formed by a plasma-enhanced CVD (PECVD) process and/or other suitable deposition or oxidation processes. Then a dielectric material layer 136 is deposited over the CES layer 134. The dielectric material layer 136 is also referred to as inter-layer dielectric (ILD) layer 136. The ILD layer 136 may include materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The ILD layer 136 may be deposited by a PECVD process or other suitable deposition technique. In an embodiment, the ILD layer 136 is formed by a flowable CVD (FCVD) process. The FCVD process includes depositing a flowable material (such as a liquid compound) over the substrate 102 to fill various trenches, and converting the flowable material to a solid material by a suitable technique, such as thermal annealing or ultra-violet radiation. The ILD layer 136 is then etched back or planarized by a CMP process to expose the hard mask layer 118.