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Source and drain surface treatment for multi-gate field effect transistors

專利號
US10868149B2
公開日期
2020-12-15
申請人
Taiwan Semiconductor Manufacturing Co., Ltd.(TW Hsinchu)
發(fā)明人
Wei-Han Fan; Wei-Yuan Lu; Yu-Lin Yang; Chun-Hsiang Fan; Sai-Hooi Yeong
IPC分類
H01L29/66; H01L29/08; H01L21/02; H01L21/265; H01L21/3065; H01L29/78; H01L21/225; H01L21/311; H01L21/306
技術(shù)領(lǐng)域
fin,in,gate,layer,etching,drain,isolation,liner,silicon,channel
地域: Hsin-Chu

摘要

A method includes providing a structure having a substrate and a fin extending from the substrate, wherein the fin includes a first semiconductor material and has a source region, a channel region, and a drain region for a transistor; forming a gate stack over the channel region; performing a surface treatment to the fin in the source and drain regions, thereby converting an outer portion of the fin in the source and drain regions into a different material other than the first semiconductor material; etching the converted outer portion of the fin in the source and drain regions, thereby reducing a width of the fin in the source and drain regions; and depositing an epitaxial layer over the fin in the source and drain regions.

說明書

Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to a semiconductor device and the formation thereof. For example, trimmed fin portions in the source/drain (S/D) regions allow source/drain features to directly contact the channel region, improving dopant diffusion efficiency. The trimming cycles also clean the exterior surfaces of the fin in the S/D regions, increasing epitaxial growth quality for the source/drain features. The fin portions remained in the S/D regions also help maintaining strain strength inside the channel region. Further, the disclosed methods can be readily integrated into existing semiconductor manufacturing processes.

權(quán)利要求

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