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Source and drain surface treatment for multi-gate field effect transistors

專利號
US10868149B2
公開日期
2020-12-15
申請人
Taiwan Semiconductor Manufacturing Co., Ltd.(TW Hsinchu)
發(fā)明人
Wei-Han Fan; Wei-Yuan Lu; Yu-Lin Yang; Chun-Hsiang Fan; Sai-Hooi Yeong
IPC分類
H01L29/66; H01L29/08; H01L21/02; H01L21/265; H01L21/3065; H01L29/78; H01L21/225; H01L21/311; H01L21/306
技術領域
fin,in,gate,layer,etching,drain,isolation,liner,silicon,channel
地域: Hsin-Chu

摘要

A method includes providing a structure having a substrate and a fin extending from the substrate, wherein the fin includes a first semiconductor material and has a source region, a channel region, and a drain region for a transistor; forming a gate stack over the channel region; performing a surface treatment to the fin in the source and drain regions, thereby converting an outer portion of the fin in the source and drain regions into a different material other than the first semiconductor material; etching the converted outer portion of the fin in the source and drain regions, thereby reducing a width of the fin in the source and drain regions; and depositing an epitaxial layer over the fin in the source and drain regions.

說明書

In one exemplary aspect, the present disclosure is directed to a method. The method includes providing a structure having a substrate and a fin extending from the substrate, wherein the fin includes a first semiconductor material and has a source region, a channel region, and a drain region for a transistor; forming a gate stack over the channel region; performing a surface treatment to the fin in the source and drain regions, thereby converting an outer portion of the fin in the source and drain regions into a different material other than the first semiconductor material; etching the converted outer portion of the fin in the source and drain regions, thereby reducing a width of the fin in the source and drain regions; and depositing an epitaxial layer over the fin in the source and drain regions. In an embodiment, the performing of the surface treatment includes an oxidization process. In an embodiment, the oxidization process is a wet oxidization process. In an embodiment, the etching of the converted outer portion of the fin also reduces a height of the fin in the source and drain regions. In an embodiment, the etching of the converted outer portion of the fin also exposes a portion of the fin in the channel region, and wherein the epitaxial layer is in direct contact with the exposed portion of the fin in the channel region. In an embodiment, the structure further includes an isolation layer covering the substrate and the etching of the converted outer portion also recesses a top surface of the isolation layer. In an embodiment, a bottom portion of the fin is covered by a liner film, and wherein after the etching of the converted outer portion of the fin, a topmost portion of the liner film is higher than the recessed top surface of the isolation layer. In an embodiment, the first semiconductor material is silicon germanium. In an embodiment, the method further includes repeating the performing of the surface treatment and the etching of the converted outer portion of the fin until the width of the fin in the source and drain regions is reduced by a predetermined value. In an embodiment, the method, before the performing of the surface treatment, further includes forming a spacer over the gate stack and over the fin in the source and drain regions; and selectively etching the spacer over the fin in the source and drain regions.

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