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Conformal transfer doping method for fin-like field effect transistor

專利號
US10868151B2
公開日期
2020-12-15
申請人
Taiwan Semiconductor Manufacturing Co., Ltd.（TW Hsinchu）
發(fā)明人
Sai-Hooi Yeong; Sheng-Chen Wang; Bo-Yu Lai; Ziwei Fang; Feng-Cheng Yang; Yen-Ming Chen
IPC分類
H01L21/265; H01L29/66; H01L21/225; H01L29/165
技術(shù)領(lǐng)域
doped,fin,finfet,amorphous,layer,fins,in,structure,knock,silicon
地域： Hsinchu

摘要

Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

說明書

The present application is a continuation application of U.S. patent application Ser. No. 15/653,720, filed Jul. 19, 2017, which claims benefit of U.S. Provisional Patent Application Ser. No. 62/434,694, filed Dec. 15, 2016, each of which is incorporated herein by reference in its entirety.

BACKGROUND

The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.

Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, as fin-like field effect transistor (FinFET) technologies progress towards smaller feature sizes (such as 32 nanometers, 28 nanometers, 20 nanometers, and below), advanced doping techniques are needed to provide doped features (regions) in fin structures having deeper, more uniform doping profiles without damaging the fin structures. Although existing FinFET doping techniques have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.

BRIEF DESCRIPTION OF THE DRAWINGS

權(quán)利要求

1
What is claimed is:1. A method comprising:forming a fin structure over a substrate;forming a gate structure over the fin structure; andforming a source/drain feature on the fin structure, wherein forming the source/drain feature includes:forming a doped layer on the fin structure; andcrystallizing at least a portion of the doped layer, wherein crystallizing at least the portion of the doped layer includes performing an implantation process to drive a dopant from the doped layer into the fin structure.2. The method of claim 1, wherein crystallizing at least a portion of the doped layer includes driving a dopant from the doped layer into a source/drain region of the fin structure.3. The method of claim 2, wherein the source/drain feature includes the portion of the crystallized doped layer and the source/drain region of the fin structure, andwherein a concentration of the dopant is substantially uniform at any point of the portion of the crystallized doped layer and the source/drain region of the fin structure, wherein the dopant concentration is considered substantially uniform when doping concentrations at any defined number of points of the portion of the crystallized doped layer and the source/drain region of the fin structure are within ±5% of each other.4. The method of claim 3, wherein the concentration of the dopant in the source/drain feature ranges from about 1×1020 cm?3 to about 5×1020 cm?3.5. The method of claim 1, further comprising reducing a width of the fin structure prior to forming the source/drain feature on the fin structure.6. The method of claim 1, wherein the source/drain feature is a lightly doped source and drain (LDD) feature.7. The method of claim 1, wherein the doped layer includes silicon.8. The method of claim 1, wherein performing the implantation process to drive the dopant from the doped layer into the fin structure includes applying a bias voltage of about 1 kV to about 5 kV to the substrate.9. A method comprising:forming a fin structure over a substrate;forming a doped layer over the fin structure, wherein the doped layer includes a material having a non-crystalline structure; andperforming an implantation process to drive a dopant from the doped layer into the fin structure, wherein the implantation process converts a first portion of the doped layer into the material having a crystalline structure.10. The method of claim 9, wherein performing the implantation process to drive the dopant from the doped layer into the fin structure includes applying a bias voltage of about 1 kV to about 5 kV to the substrate.11. The method of claim 9, wherein a concentration of the dopant in the fin structure ranges from about 1×1020 cm?3 to about 5×1020 cm?3.12. The method of claim 9, further comprising forming a gate structure over a channel region of the fin structure before performing the implantation process, andwherein forming the doped layer over the fin structure includes forming the doped layer over a source/drain region of the fin structure.13. A method comprising:forming a fin structure over a substrate;forming a gate structure over the fin structure;forming a doped layer over the fin structure, wherein the doped layer has a non-crystalline structure; andperforming a knock-on implantation process to drive a dopant from the doped layer into the fin structure, wherein the knock-on implantation process converts a portion of the doped layer into a crystalline structure.14. The method of claim 13, wherein the fin structure includes crystalline silicon germanium and the doped layer includes non-crystalline silicon.15. The method of claim 13, wherein the doped layer is formed on a source/drain region of the fin structure, and the doped layer forms a heavily doped source/drain (HDD) region disposed in the source region and the drain region of the fin structure.16. The method of claim 13, wherein a concentration of the dopant in the doped layer ranges from about 1×1021 cm?3 to about 4×1021 cm?3 and a concentration of the dopant in the fin structure ranges from about 1×1010 cm?3 to about 1×1018 Cm?3.17. The method of claim 13 further comprising:oxidizing a remaining portion of the doped layer after performing the knock-on implantation process; andremoving the oxidized remaining portion of the doped layer.18. The method of claim 13 further comprising reducing a width of the fin structure prior to forming the doped layer over the fin structure.19. The method of claim 18, further comprising reducing a height of the fin structure at a same rate as reducing the width of the fin structure.20. The method of claim 13 further comprising forming an isolation feature over the substrate prior to forming the doped layer over the fin structure.
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