A combination of deposition, lithography, and/or etching processes are performed to define fins 222 extending from substrate 210 as illustrated in FIG. 2A. For example, forming fin structure 220 includes performing a lithography process to form a patterned resist layer over substrate 210 (or a material layer disposed over substrate 210) and performing an etching process to transfer a pattern defined in the patterned resist layer to substrate 210 (or the material layer disposed over substrate 210). The lithography process can include forming a resist layer on substrate 210 (for example, by spin coating), performing a pre-exposure baking process, performing an exposure process using a mask, performing a post-exposure baking process, and performing a developing process. During the exposure process, the resist layer is exposed to radiation energy (such as ultraviolet (UV) light, deep UV (DUV) light, or extreme UV (EUV) light), where the mask blocks, transmits, and/or reflects radiation to the resist layer depending on a mask pattern of the mask and/or mask type (for example, binary mask, phase shift mask, or EUV mask), such that an image is projected onto the resist layer that corresponds with the mask pattern. Since the resist layer is sensitive to radiation energy, exposed portions of the resist layer chemically change, and exposed (or non-exposed) portions of the resist layer are dissolved during the developing process depending on characteristics of the resist layer and characteristics of a developing solution used in the developing process. After development, the patterned resist layer includes a resist pattern that corresponds with the mask. The etching process removes portions of substrate 210, where the etching process uses the patterned resist layer as an etch mask. The etching process can include a dry etching process, a wet etching process, other suitable etching process, or combinations thereof. In some implementations, a reactive ion etching (RIE) process is performed. After the etching process, the patterned resist layer is removed from substrate 210, for example, by a resist stripping process. Alternatively, fin structure 220 is formed by a multiple patterning process, such as a double patterning lithography (DPL) process (for example, a lithography-etch-lithography-etch (LELE) process, a self-aligned double patterning (SADP) process, a spacer-is-dielectric (SID) SADP process, other double patterning process, or combinations thereof), a triple patterning process (for example, a lithography-etch-lithography-etch-lithography-etch (LELELE) process, a self-aligned triple patterning (SATP) process, other triple patterning process, or combinations thereof), other multiple patterning process (for example, self-aligned quadruple patterning (SAQP) process), or combinations thereof. In some implementations, directed self-assembly (DSA) techniques are implemented while forming fin structure 220. Further, in some alternate implementations, the exposure process can implement maskless lithography, electron-beam (e-beam) writing, ion-beam writing, and/or nanoimprint technology for patterning the resist layer.