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Conformal transfer doping method for fin-like field effect transistor

專利號
US10868151B2
公開日期
2020-12-15
申請人
Taiwan Semiconductor Manufacturing Co., Ltd.(TW Hsinchu)
發(fā)明人
Sai-Hooi Yeong; Sheng-Chen Wang; Bo-Yu Lai; Ziwei Fang; Feng-Cheng Yang; Yen-Ming Chen
IPC分類
H01L21/265; H01L29/66; H01L21/225; H01L29/165
技術(shù)領(lǐng)域
doped,fin,finfet,amorphous,layer,fins,in,structure,knock,silicon
地域: Hsinchu

摘要

Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

說明書

Similar to FinFET device 200, FinFET device 400 includes substrate 210 and fin structure 220, which includes fins 222 extending from substrate 210. In FIG. 4, fins 222 extend from substrate 210 in a z-direction, such that fins 222 have heights defined in the z-direction (such as height h), lengths defined in an x-direction, and widths and/or spacings defined in a y-direction (such as width w1, width w2, width w3, spacing S1, spacing S2, and spacing S3). Each fin 222 has a channel region 402, a source region 404, and a drain region 406 defined along the length of respective fins 222 (here, along the x-direction), where channel region 402 is disposed between source region 404 and drain region 406 (generally referred to as source/drain regions). Each channel region 402 includes a top portion defined between sidewall portions of a respective fin 222, where the top portion and the sidewall portions engage with a gate structure 410 (described in detail below), such that current can flow between a respective source region 404 and a respective drain region 406 during operation of FinFET device 400. In FIG. 4, gate structure 410 blocks view of channel regions 402 of fins 222. In some implementations, the top portion is a substantially horizontal side (for example, substantially parallel to an x-y plane) of fins 222, while the two sidewall portions are substantially vertical sides (for example, substantially parallel to an x-z plane) of fins 222.

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