Further, in such implementations, before forming doped amorphous layer 230, gate structure 410 can be formed over fin structure 220. Gate structure 410 wraps channel regions 402 of fins 222, thereby engaging fins 222 and interposing source regions 404 and drain regions 406. In the depicted embodiment, gate structure 410 engages the top portion and the sidewall portions of channel regions 402, such that gate structure 410 engages three sides of channel regions 402. Gate structure 410 includes a dummy gate stack, portions of which can be replaced with a metal gate during a gate replacement process as described in detail below. In the depicted embodiment, the dummy gate stack includes a gate dielectric 430 and a gate electrode 432. Gate dielectric 430 is disposed between gate electrode 432 and fins 222, where gate dielectric 430 and gate electrode 432 are configured to wrap fins 222 (in particular, channel regions 402). Gate dielectric 430 includes a dielectric material, such as silicon oxide, a high-k dielectric material, other suitable dielectric material, or combinations thereof. Examples of high-k dielectric material include HfO₂, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-alumina (HfO₂—Al₂O₃) alloy, other suitable high-k dielectric materials, or combinations thereof. Gate electrode 432 includes a suitable dummy gate material, such as polysilicon. The dummy gate stack can include numerous other layers, for example, capping layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. In some implementations, the dummy gate stack further includes an interfacial layer, such as a silicon oxide layer, disposed between gate dielectric 430 and gate electrode 432. In some implementations, a capping layer, such as a TiN capping layer, can be disposed between gate dielectric 430 and gate electrode 432.