FinFET device 400 and/or FinFET device 500 can undergo further processing. For example, spacers can be formed adjacent to gate structure 410 (here, gate dielectric 430 and gate electrode 432). The spacers include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, other suitable material, or combinations thereof. In some implementations, the spacers include a multi-layer structure, such as a silicon nitride layer and a silicon oxide layer. The spacers are formed by any suitable process. In some implementations, spacers include more than one set of spacers, such as seal spacers, offset spacers, dummy spacers and/or main spacers formed adjacent to the dummy gate stack. In such implementations, the various sets of spacers can include materials having different etching rates. For example, a silicon oxide layer can be deposited over fin structure 220 and subsequently anisotropically etched (for example, dry etched) to form a first spacer set adjacent to the dummy gate stack, and a silicon nitride layer can be deposited over fin structure 220 and subsequently etched (for example, dry etched) to form a second spacer set adjacent to the first spacers set.