A metal gate stack of gate structure 410 is then formed in the opening (trench). The metal gate stack includes a gate dielectric and a gate electrode (for example, a work function layer and a metal fill layer). The metal gate stack of gate structure 410 may include numerous other layers, for example, capping layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. In some implementations, a gate dielectric layer is formed over the interfacial layer, and a gate electrode layer (such as a work function fill layer and a metal fill layer) is formed over the gate dielectric layer. The gate dielectric layer includes a dielectric material, such as silicon oxide, high-k dielectric material, other suitable dielectric material, or combinations thereof. Examples of high-k dielectric material include HfO₂, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-alumina (HfO₂—Al₂O₃) alloy, other suitable high-k dielectric materials, or combinations thereof. In some implementations, the gate dielectric layer is a high-k dielectric layer. In some implementations, where an interfacial layer is omitted from the dummy gate stack, the gate dielectric layer can include an interfacial layer (such as a silicon oxide layer), and a high-k dielectric layer disposed over the interfacial layer. The gate electrode includes a conductive material, such as polysilicon, Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive material, or combinations thereof. In some implementations, the work function layer is a conductive layer tuned to have a desired work function (such as an n-type work function or a p-type work function), and the metal fill layer is a conductive layer formed over the work function layer. In some implementations, the work function layer includes n-type work function materials, such as Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. In some implementations, the work function layer includes a p-type work function material, such as TiN, TaN, Ru, Mo, Al, WN, ZrSi₂, MoSi₂, TaSi₂, NiSi₂, WN, other suitable p-type work function materials, or combinations thereof. The metal fill layer includes a suitable conductive material, such as aluminum, tungsten, or copper. The metal fill layer may additionally or collectively include polysilicon, titanium, tantulum, metal alloys, other suitable materials, or combinations thereof. The gate dielectric layer, the work function layer, and the metal fill layer are formed by various deposition processes, such as ALD, CVD, PVD, and/or other suitable process. In some implementations, the work function layer and the metal fill layer may conform to exposed surfaces in the opening. CMP process can be performed to remove excess material (such as any excess work function layer and/or any excess metal fill layer), planarizing gate structure 410.