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Conformal transfer doping method for fin-like field effect transistor

專利號
US10868151B2
公開日期
2020-12-15
申請人
Taiwan Semiconductor Manufacturing Co., Ltd.(TW Hsinchu)
發(fā)明人
Sai-Hooi Yeong; Sheng-Chen Wang; Bo-Yu Lai; Ziwei Fang; Feng-Cheng Yang; Yen-Ming Chen
IPC分類
H01L21/265; H01L29/66; H01L21/225; H01L29/165
技術(shù)領(lǐng)域
doped,fin,finfet,amorphous,layer,fins,in,structure,knock,silicon
地域: Hsinchu

摘要

Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

說明書

In implementations where a portion of the doped amorphous layer becomes a part of the fin structure, method 100 can proceed with removing a remaining portion of the doped amorphous layer. In such implementations, removing the remaining portion of the doped amorphous layer can include oxidizing the remaining portion of the doped amorphous layer, and performing a wet etching process and/or a cleaning process to remove the oxidized remaining portion. In some implementations, before forming the doped amorphous layer, a trimming process is performed to reduce a dimension (such as a width) of the fin structure. In such implementations, the knock-on implantation process converts the entire doped amorphous layer into a part of the fin structure (in other words, into crystalline material), such that no portion of the doped amorphous layer remains. Such implementations eliminate the need for any subsequent wet etching process and/or subsequent cleaning process. In some implementations, a thickness of the doped amorphous layer is equal to a thickness (or width) of the fin structure removed during the trimming process.

At block 140, method 100 can continue to complete fabrication of the FinFET device. For example, in implementations where the gate structure includes a dummy gate, a gate replacement process is performed to replace the dummy gate with a metal gate. In implementations where the doped feature defines an active region of the FinFET device, method 100 can proceed with forming additional IC features to fabricate a functional FinFET device. Additional steps can be provided before, during, and after method 100, and some of the steps described can be moved, replaced, or eliminated for additional embodiments of method 100. The discussion that follows illustrates various embodiments of FinFET devices that can be fabricated according to method 100.

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