Highly strained source/drain trenches in semiconductor devices
地域：
Sijhih
摘要
A semiconductor device is formed by a multi-step etching process that produces trench openings in a silicon substrate immediately adjacent transistor gate structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms the openings. The openings are bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The openings may be filled with a suitable source/drain material to produce SSD transistors with desirable Idsat characteristics.
說明書
This application is a divisional application of U.S. patent application Ser. No. 12/428,905, filed on Apr. 23, 2009, the contents of which are hereby incorporated by reference as if set forth in their entirety.
The present invention relates, most generally, to semiconductor devices and methods for forming the same. More particularly, the present invention relates to methods for forming trenches for highly strained source/drain regions in semiconductor transistor devices and the transistor devices so formed.
In today's rapidly advancing semiconductor manufacturing industry, there is a continuing push to produce smaller, faster and more efficient semiconductor devices. One such device that this principle applies to is the transistor device. Transistor devices may be manufactured by forming transistor gate structures including a transistor gate and sidewall spacers, over a substrate surface then forming openings in the substrate then filling the openings to produce source/drain regions. The substrate is typically formed of bulk, single crystal silicon that may include various lattice orientations. After these substrate openings are formed, selected epitaxial growth, SEG, or other deposition techniques may be used to fill the openings with SiGe or other suitable materials that will serve as the source/drain regions for the transistors or other semiconductor devices formed over the surface. The source/drain regions may then be silicided.
權利要求
What is claimed is:1. A semiconductor device, comprising:a silicon substrate with a plurality of openings extending downwardly from a substrate surface of said silicon substrate and defining a silicon mesas between respective two openings of said plurality of openings, each silicon mesas comprising a top surface that is a portion of said substrate surface, at least one upper surface portion bordering the top surface and having a substantially vertical side surface, and at least one concave lower surface portion that borders the at least one upper surface portion and curves under the top surface; a plurality of transistor structures, each transistor structure of said plurality of transistor structures formed above said top surface of a corresponding one of said silicon mesas, each transistor structure of said plurality of transistor structures including a transistor gate and respective sidewall spacers contacting opposed sidewalls of said transistor gate and contacting a hard mask on top of said transistor gate; and a source/drain structure disposed between a first transistor gate and a second transistor gates of said plurality of transistor structures, the first transistor gate and the second transistor gates being immediately adjacent to one another, wherein the source/drain structure comprises: a first vertical sidewall portion aligned with a vertical sidewall of a first sidewall spacer formed on a sidewall of the first transistor gate; a second vertical sidewall portion aligned with a vertical sidewall of a second sidewall spacer formed on a sidewall of the second transistor gate; a first curved sidewall portion extending from the first vertical sidewall portion and curving inwardly toward the first transistor gate so as to undercut the first sidewall spacer; a second curved sidewall portion extending from the second vertical sidewall portion and curving inwardly toward the second transistor gate so as to undercut the second sidewall spacer; a flat top surface that is coplanar with the top surface of the silicon substrate; and a flat bottom surface disposed between and connecting a bottom portions of each of the first curved sidewall portion and the second curved sidewall portion. 2. The semiconductor device as in claim 1 , wherein said substantially vertical side first vertical sidewall portion and said second vertical sidewall portions each extends downwardly from said top surface for at least about 7 nanometers. 3. The semiconductor device as in claim 1 , wherein each transistor gates include a first width and each silicon mesas include a minimum width being at least 20 nanometers less than said first width. 4. The semiconductor device as in claim 1 , wherein said single continuous source/drain material is formed of silicon germanium. 5. The semiconductor device as in claim 1 , wherein each transistor gate is formed of polycrystalline silicon. 6. The semiconductor device as in claim 1 , wherein said sidewall spacers are each formed of silicon nitride. 7. The semiconductor device as in claim 1 , wherein said source/drain structure is formed of a material that is configured to be silicided. 8. The semiconductor device as in claim 1 , wherein said source/drain structure is formed of a silicide. 9. The semiconductor device as in claim 1 , wherein each of said first vertical sidewall portion and said second vertical sidewall portion extends downwardly from said top surface for 5 nanometers to 15 nanometers. 10. A semiconductor device, comprising:a semiconductor substrate with a plurality of openings extending downwardly from a top surface of the semiconductor substrate, each of said plurality of openings bounded and defined by substantially vertical side semiconductor surfaces extending downwardly from said top surface and concave side semiconductor surfaces which meet located below respective ones of said substantially vertical side semiconductor surfaces; a pair of transistor structures formed above said top surface, each of said pair of transistor structures including a transistor gate and a pair of opposed sidewall spacers contacting respective ones of opposed sidewalls of said transistor gate and contacting a hard mask on top of said transistor gate; and a source/drain structure disposed between a first transistor gate and a second transistor gates of said pair of transistor structures, the first transistor gate and the second transistor gates being immediately adjacent to one another, wherein the source/drain structure comprises: a first vertical sidewall portion aligned with a vertical sidewall of a first sidewall spacer formed on a sidewall of the first transistor gate; a second vertical sidewall portion aligned with a vertical sidewall of a second sidewall spacer formed on a sidewall of the second transistor gate; a first curved sidewall portion extending from the first vertical sidewall portion and curving inwardly toward the first transistor gate so as to undercut the first sidewall spacer; a second curved sidewall portion extending from the second vertical sidewall portion and curving inwardly toward the second transistor gate so as to undercut the second sidewall spacer; a flat top surface that is coplanar with the top surface of the silicon substrate; and a flat bottom surface disposed between and connecting a bottom portions of each of the first curved sidewall portion and the second curved sidewall portions. 11. The semiconductor device as in claim 10 , wherein said semiconductor substrate is a silicon substrate. 12. The semiconductor device as in claim 10 , wherein said substrate opening extends underneath said pair of transistor structures and laterally inward by at least 11 nanometers. 13. The semiconductor device as in claim 10 , wherein source/drain structure is formed of a material comprising silicon germanium. 14. The semiconductor device as in claim 13 , wherein said source/drain structure is formed of a material comprising silicide. 15. The semiconductor device as in claim 10 , wherein said each sidewall spacer is formed of a material comprising silicon nitride. 16. The semiconductor device as in claim 10 , wherein each of said first vertical sidewall portion and said second vertical sidewall portion extends downwardly from said top surface for 5 nanometers to 15 nanometers. 17. The semiconductor device as in claim 10 , wherein each of said first vertical sidewall portion and said second vertical sidewall portion extends downwardly from said top surface for at least 7 nanometers.
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