According to various conventional methods, the openings formed in the substrate are formed using the structures formed over the semiconductor substrate, e.g. the transistor gate structures, as self-aligned mask structures. The openings have a profile determined by the etching process used to produce the openings which may undercut the transistor gate or other self-aligned mask structures. The etching process significantly impacts the degree of undercut and the stress level of the etched silicon, and the stress level has a profound influence upon I_dsat performance. When forming the substrate openings that will be used for source/drain regions in transistor devices, it is advantageous to use aggressive isotropic etch processes to produce an increased tensile stress, as this improves hole mobility in the formed devices. It is known that extended isotropic etch times desirably extend the lateral encroachment, i.e. undercut of the opening and produce increased tensile stress levels in the etched silicon surfaces created. By increasing the isotropic etch step time, however, the degree of undercut of the surface immediately beneath the edge of the self-aligned masking structure formed over the surface, is undesirably increased. As a result, attack and erosion of the overlying structures undesirably occurs and pull-back of the edge of the opening undesirably occurs. When the masking structure is a transistor gate with SiN sidewall spacers, the aggressive isotropic etch may attack the spacers, recede the edges of the spacers and pull-back the substrate surface immediately beneath the edges of the spacers. This undesirably results in significant SCE (short channel effects).