A gate trench 140 is arranged in the cell mesa region 120 formed by the upper drift region 153a between adjacent spicular trenches 130. The gate trench 140 extends from the first side 101 through the source region 151 and the body region 152 into the drift region 153. As seen in the cross-sectional view of FIG. 3, the spicular trenches 130 are much deeper than the respective gate trenches 140, which merely extend slightly deeper into the semiconductor substrate 100 than a lower end of the body region 152. The lower end of the gate trenches 140 are therefore slightly below the first pn-junction between the drift region 153 and the body region 152. The gate trench 140 may form, when seen in plan projection onto the first side 101, a net or a grid of crossing gate trenches. When seen in a vertical cross-sectional view as in FIG. 3, the gate trenches 140 may appear to be separated although they are connected with each other at gate crossing regions.

Each gate trench 140 includes a gate electrode 141 which is electrically insulated from the surrounding semiconductor substrate 100 by a gate dielectric 142. The gate dielectric 142 is typically much thinner than the field oxide 131 of the spicular trench 130, because the gate dielectric 142 needs to tolerate only moderate voltages such as 5 V to 15 V. Different thereto, the field oxide 131 needs to withstand much higher voltages, such as 50 V to 250 V or above, particularly in the region at the bottom of the spicular trenches 130.