Field effect transistor contact with reduced contact resistance using implantation process
地域：
Hsinchu
摘要
Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.
說(shuō)明書(shū)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
This application is a continuation of U.S. application Ser. No. 16/504,670, filed on Jul. 8, 2019, entitled “Field Effect Transistor Contact with Reduced Contact Resistance Using Implantation Process”, which is a divisional of U.S. application Ser. No. 15/991,570, filed on May 29, 2018, now U.S. Pat. No. 10,347,762 issued Jul. 9, 2019, entitled “Field Effect Transistor Contact with Reduced Contact Resistance Using Implantation Process”, each application is hereby incorporated herein by reference.
As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a Fin Field Effect Transistor (FinFET). FinFET devices typically include semiconductor fins with high aspect ratios and in which channel and source/drain regions are formed. A gate is formed over and along the sides of the fin structure (e.g., wrapping) utilizing the advantage of the increased surface area of the channel to produce faster, more reliable, and better-controlled semiconductor transistor devices.
FinFET devices typically include semiconductor regions used to form source regions and drain regions. Metal silicides are then formed on the surfaces of the semiconductor regions in order to reduce the contact resistance. However, with the decreasing in scaling, new challenges are presented.
權(quán)利要求
What is claimed is:1. A semiconductor device comprising:an active area on a substrate, the active area comprising a source/drain region, the source/drain region having a silicide layer disposed on a semiconductor material, the source/drain region comprising:a first region proximate a top surface of the source/drain region and overlapped with at least a portion of the silicide layer, the first region comprising a first species and a second species, the first species being an ion of a Group III element that has a larger atomic radius than the second species, wherein a peak concentration of the first species being proximate the top surface of the source/drain region, a concentration of first species decreasing in the source/drain region from the peak concentration of the first species in a direction away from the top surface of the source/drain region, wherein the second species has a conductivity type; and a dielectric layer over the active area; and a conductive feature extending through the dielectric layer to the active area and contacting the source/drain region at the silicide layer. 2. The device of claim 1 , wherein the semiconductor material comprises silicon germanium, wherein the first region has a first concentration of germanium. 3. The device of claim 2 , wherein the source/drain region further comprises a second region below the first region, the second region having a second concentration of germanium lower than the first concentration of germanium. 4. The device of claim 3 , wherein the first region is completely contained within the second region. 5. The device of claim 3 , wherein the first concentration of germanium is in a range from about 20 atomic percent (at. %) to about 100 at. %, and the second concentration of germanium is in a range from about 0 at. % to about 20 at. %. 6. The device of claim 1 , wherein the first species comprises gallium and the second species comprises a p-type dopant. 7. The device of claim 1 , wherein the second species has a peak concentration at a vertical depth in a range of about 2 nm to about 4 nm. 8. A semiconductor device comprising:a fin protruding from a substrate, the fin comprising a first semiconductor material; a first gate structure over the fin, wherein the fin comprises a channel region under the fin; a second semiconductor material adjacent the channel region, the second semiconductor material being different than the first semiconductor material, the second semiconductor material further comprising:a first species having a first species concentration that increases to a first peak concentration within 1 to 3 nm of a surface of the first semiconductor material in a direction away from a top surface of the second semiconductor material; and a second species having a second species concentration that increases within at a depth of 2 nm to 4 nm in the direction away from the top surface of the second semiconductor material, the first species being different than the second species, the second species having a conductivity type; and a silicide region in the second semiconductor material. 9. The device of claim 8 , wherein the first species has an atomic radius larger than the second species. 10. The device of claim 9 , wherein first species comprises ion of a Group III element. 11. The device of claim 10 , wherein the first species comprises gallium and the second species comprises boron. 12. The device of claim 8 , wherein the first peak concentration of the first species is about 1×1022 A/cm3 or greater. 13. The device of claim 8 , wherein the second semiconductor material extends laterally past boundaries of the first species concentration along opposite directions. 14. The device of claim 13 , wherein the first species extends laterally past opposite boundaries of the silicide region. 15. A semiconductor device comprising:a first gate structure over a fin, the fin comprising a first semiconductor material; a source/drain region over the fin adjacent the first gate structure, the source/drain region comprising a second semiconductor material, wherein the source/drain region comprises a first species and a second species in the second semiconductor material, wherein the second species has a first conductivity type, wherein a concentration of the first species increases along a direction away from an upper surface of the source/drain region to a first peak concentration in a range of 1 nm to 3 nm of a surface of the source/drain region, wherein a concentration of the second species piles up to a second peak concentration at a depth of 2 nm to 4 nm from the surface of the source/drain region; a first dielectric layer over the first gate structure and the source/drain region; a contact extending through the first dielectric layer, the contact being electrically coupled to the source/drain region; and a silicide region interposed between the contact and the source/drain region. 16. The device of claim 15 , wherein the silicide region is contained within a region of the source/drain region having the first species. 17. The device of claim 16 , wherein the first species comprises ion of a Group III element and the second species comprises a p-type dopant. 18. The device of claim 15 , wherein the second semiconductor material comprises silicon germanium, wherein a first region has a first germanium concentration and a second region has a second germanium concentration lower than the first germanium concentration, wherein the first region is contained within the second region. 19. The device of claim 18 , wherein the first germanium concentration is in a range from about 20 atomic percent (at. %) to about 100 at. %, and the second germanium concentration is in a range from about 0 at. % to about 20 at. %. 20. The device of claim 18 , wherein the first species is contained within the first region.
意見(jiàn)反饋
使用該功能遇到問(wèn)題
該功能需要專業(yè)版企業(yè)版VIP權(quán)限，您可以：
您也可以聯(lián)系官方QQ: 2157717237 電話: 13264338900