Referring to FIG. 4, a contact etch stop layer (CESL) 296 and a first interlayer dielectric (ILD) 297 are sequentially formed on surfaces of the source/drain regions 292, sidewalls and top surfaces of the gate spacers 286, top surfaces of the masks 284, and top surfaces of the isolation regions 278 using any suitable deposition technique. The CESL 296 is deposited conformally and may include or be silicon nitride, silicon carbon nitride, carbon nitride, the like, or a combination thereof. The first ILD 297 may include or be tetraethylorthosilicate (TEOS) oxide, silicon dioxide, a low-k dielectric material (e.g., a material having a dielectric constant lower than silicon dioxide), or the like. A chemical mechanical planarization (CMP) process may then be performed to planarize the first ILD 297 and the CESL 296 and to remove the masks 284 of the dummy gate structures 251, thereby leveling the top surface of the first ILD 297 and CESL 296 with the top surfaces of the dummy gates 282.