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Field effect transistor contact with reduced contact resistance using implantation process

專利號
US10868178B2
公開日期
2020-12-15
申請人
Taiwan Semiconductor Manufacturing Co., Ltd.(TW Hsinchu)
發(fā)明人
Su-Hao Liu; Kuo-Ju Chen; Chun-Hung Wu; Chia-Cheng Chen; Liang-Yin Chen; Huicheng Chang; Ying-Lang Wang
IPC分類
H01L29/165; H01L29/78; H01L27/088; H01L21/3115; H01L29/66; H01L21/8234; H01L21/02; H01L21/3215; H01L29/161
技術(shù)領域
drain,regions,gallium,source,dopant,in,species,may,layer,germanium
地域: Hsinchu

摘要

Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.

說明書

As can be seen in the second profile 1014, when gallium was used to amorphorize the source/drain region, boron has a greater concentration (pile up) at a depth in a range from about 2 to about 4 nm than the first profile 1012 where boron was first used to amorphorize the source/drain region. The second profile 1014 suggests that boron dopants are largely trapped in the amorphous regions due to the presence of implanted gallium from the PAI process. Therefore, when gallium was implanted preceding the dopant (e.g., boron) implant, a higher dopant concentration can be created proximate the surface of the source/drain region. The third profile 1016 shows gallium has a peak concentration of about 1×1022 A/cm3 at or proximate the surface of the source/drain region (at a depth in a range from about 1 to about 3 nm) due to its larger size on an atomic scale and higher solid solubility in germanium.

While the device structures may vary in different embodiments, it is contemplated that various embodiments in this disclosure can be applied to FinFETs having fins on a crown structure. FIG. 11 illustrates a cross-sectional view of a portion of a device structure in accordance with some embodiments. The structure of FIG. 11 may be referred to as a “crown” structure, whereas the structure of, e.g., FIG. 1 may be referred to as a “non-crown” structure. As depicted in FIG. 11, the lower surfaces of the isolation regions 278 may be at varying levels. This may be obtained during patterning the semiconductor substrate 270 in forming the fins 274, such as by two or more patterning and etching processes.

權(quán)利要求

1
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