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Field effect transistor contact with reduced contact resistance using implantation process

專利號
US10868178B2
公開日期
2020-12-15
申請人
Taiwan Semiconductor Manufacturing Co., Ltd.(TW Hsinchu)
發(fā)明人
Su-Hao Liu; Kuo-Ju Chen; Chun-Hung Wu; Chia-Cheng Chen; Liang-Yin Chen; Huicheng Chang; Ying-Lang Wang
IPC分類
H01L29/165; H01L29/78; H01L27/088; H01L21/3115; H01L29/66; H01L21/8234; H01L21/02; H01L21/3215; H01L29/161
技術(shù)領(lǐng)域
drain,regions,gallium,source,dopant,in,species,may,layer,germanium
地域: Hsinchu

摘要

Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.

說明書

In another embodiment, a method for semiconductor processing is provided. The method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium having a concentration of about 20 atomic percent (at. %) or greater, forming a dielectric layer over the active area, forming an opening through the dielectric layer to expose at least a portion of an upper surface of the source/drain region, implanting a first species comprising gallium into the exposed source/drain region, after implanting the first species, implanting a second species comprising a p-type dopant into the exposed source/drain region, subjecting the exposed source/drain region to a first anneal process operating at a first temperature window for a first duration, after the first anneal process, subjecting the exposed source/drain region to a second anneal process operating at a second temperature window for a second duration, the second temperature being higher than the first temperature window and the second duration being shorter than the first duration, forming a silicide region at the upper surface of the exposed source/drain region, and forming a conductive feature in the opening to the upper surface of the source/drain region.

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