FIGS. 2-9 are schematic cross-sectional views of respective intermediate structures corresponding to various stages of fabrication and corresponding to cross-section A-A in FIG. 1. Cross-section A-A in FIG. 1 is in a plane along, e.g., channels in the fin 274 between opposing source/drain regions 292.

FIG. 2 illustrates gate spacers 286 formed along sidewalls of the dummy gate structures 251 (e.g., sidewalls of the interfacial dielectrics 280, dummy gates 282, and masks 284) and over the fins 274. The gate spacers 286 may be formed by conformally depositing one or more layers for the gate spacers 286 and anisotropically etching the one or more layers, for example. The one or more layers for the gate spacers 286 may include a material different from the material(s) for the dummy gate structure 251. In some embodiments, the gate spacer 286 may include or be a dielectric material, such as silicon nitride, silicon oxynitride, silicon carbon nitride, the like, multi-layers thereof, or a combination thereof, and may be deposited by any suitable deposition technique.