Field effect transistor contact with reduced contact resistance using implantation process
地域：
Hsinchu
摘要
Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.
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After the gate spacers 286 are formed, source/drain regions 292 may be formed in the fins 274 on opposing sides of the dummy gate structures 251, as shown in
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