Fin-type field effect transistor structure and manufacturing method thereof
地域：
Hsinchu
摘要
A fin-type field effect transistor comprising a substrate, a plurality of insulators, at least one gate stack and strained material portions is described. The substrate has a plurality of fins thereon and the fin comprises a stop layer embedded therein. The plurality of insulators is disposed on the substrate and between the plurality of fins. The at least one gate stack is disposed over the plurality of fins and on the plurality of insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.
說明書
This application is a continuation application of and claims the priority benefit of U.S. patent application Ser. No. 16/214,156, filed Dec. 10, 2018, and claims the priority benefit of U.S. patent application Ser. No. 15/665,395, filed Jul. 31, 2017, now issued as U.S. Pat. No. 10,192,987B2 and U.S. patent application Ser. No. 14/883,636, filed Oct. 15, 2015, now issued as U.S. Pat. No. 9,722,079B2. The entirety of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
As the semiconductor devices keep scaling down in size, three-dimensional multi-gate structures, such as the fin-type field effect transistor (FinFET), have been developed to replace planar CMOS devices. A structural feature of the FinFET is the silicon-based fin that extends upright from the surface of the substrate, and the gate wrapping around the channel further provides better electrical control over the channel.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
權(quán)利要求
What is claimed is:1. A fin-type field effect transistor, comprising:a semiconductor substrate having fins and insulators disposed between the fins, wherein at least one fin of the fins comprises a material layer embedded within the at least one fin; at least one gate stack, disposed across the fins, wrapping around channel regions of the fins, and disposed on the insulators; and strained material portions, disposed on two opposite sides of the at least one gate stack and disposed on the fins, wherein the material layer is located below the channel region of the at least one fin and sandwiched between the strained material portions, and the material layer is located below top surfaces of the insulators. 2. The transistor of claim 1 , wherein a material of the material layer comprises silicon germanium oxide (SiGeOx), silicon germanium (SiGe), silicon oxide (SiOx), silicon phosphide (S P), silicon phosphate (SiPOx) or a combination thereof. 3. The transistor of claim 1 , wherein the material layer in the at least one fin is located above bottoms of the strained material portions. 4. The transistor of claim 1 , wherein the material layer in the at least one fin is leveled with bottoms of the strained material portions. 5. The transistor of claim 1 , wherein the strained material portions physically contact portions of the at least one fin that are not covered by the at least one gate stack without the material layer located there-between. 6. The transistor of claim 1 , wherein portions of the strained material portions below the top surfaces of the insulators have substantially vertical side profiles relatively to the top surfaces of the insulators. 7. The transistor of claim 1 , wherein portions of the strained material portions below the top surfaces of the insulators have a bottom critical dimension, a middle critical dimension larger than the bottom critical dimension, and a top critical dimension substantially equivalent to the middle critical dimension. 8. The transistor of claim 1 , wherein portions of the strained material portions below the top surfaces of the insulators have a bottom critical dimension, a middle critical dimension smaller than the bottom critical dimension, and a top critical dimension smaller than the middle critical dimension. 9. The transistor of claim 1 , wherein portions of the strained material portions below the top surfaces of the insulators have a bottom critical dimension, a middle critical dimension larger than the bottom critical dimension, and a top critical dimension smaller than the middle critical dimension. 10. A method for forming a fin-type field effect transistor, comprising:providing a semiconductor substrate; forming a material layer embedded within the semiconductor substrate, wherein a material of the material layer is different from a material of the semiconductor substrate; etching the semiconductor substrate to define fins in the semiconductor substrate by forming trenches penetrating through the material layer; filling insulators in the trenches of the semiconductor substrate, wherein top surfaces of the insulators are higher than the material layer; forming a stack structure over and across the fins and on the insulators; etching the fins using the stack structure as a mask and using the material layer as an etching stop layer to form recesses in the fins; forming strained material portions in the recesses between the insulators and at two opposite sides of the stack structure; and replacing the stack structure with a gate stack over and across the fins, between the strained material portions and on the insulators. 11. The method of claim 10 , wherein forming a material layer comprises performing ion implantation to the semiconductor substrate to form the material layer embedded within the semiconductor substrate. 12. The method of claim 10 , wherein forming a material layer comprises performing atomic layer deposition to form the material layer and then forming a silicon layer on the material layer. 13. The method of claim 10 , wherein etching the fins using the stack structure as a mask and using the material layer as an etching stop layer to form recesses comprises performing at least one anisotropic etching process to remove portions of the fins that are not covered by the stack structure until at least the material layer is removed, and the recesses in the fins have substantially vertical side profiles. 14. The method of claim 10 , wherein etching the fins using the stack structure as a mask and using the material layer as an etching stop layer to form recesses comprises performing an anisotropic etching process and then an isotropic etching process to remove portions of the fins that are not covered by the stack structure until at least the material layer is removed. 15. The method of claim 10 , wherein etching the fins using the stack structure as a mask and using the material layer as an etching stop layer to form recesses comprises performing a main etching process and then a lateral etching process to remove portions of the fins that are not covered by the stack structure until at least the material layer is removed. 16. The method of claim 10 , wherein etching the fins using the stack structure as a mask and using the material layer as an etching stop layer to form recesses comprises performing an isotropic etching process and then an anisotropic etching process to remove portions of the fins that are not covered by the stack structure until at least the material layer is removed. 17. A method, comprising:providing a semiconductor substrate; forming a material layer embedded within the semiconductor substrate, wherein a material of the material layer is different from a material of the semiconductor substrate; etching the semiconductor substrate to form trenches penetrating through the material layer and define fins between the trenches in the semiconductor substrate; filling insulators in the trenches of the semiconductor substrate, wherein top surfaces of the insulators are higher than the material layer; masking portions of the fins with a stack structure; removing unmasked portions of the fins using the material layer as an etching stop layer to form recesses in the fins; forming strained material portions in the recesses between the insulators and at two opposite sides of the stack structure; and forming a gate over and across the fins, between the strained material portions and on the insulators. 18. The method of claim 17 , further comprising implanting the strained material portions to form source and drain regions. 19. The method of claim 18 , further comprising forming silicide top layers on the source and drain regions by silicidation. 20. The method of claim 17 , wherein removing unmasked portions of the fins using the material layer as an etching stop layer to form recesses in the fins comprises etching the fins and penetrating through the material layer.
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