FIG. 2C is a perspective view of the FinFET 20 at one of various stages of the manufacturing method, and FIG. 3C is a cross-sectional view of the FinFET 20 taken along the line I-I′ of FIG. 2C. In Step 14, insulators 114 filled within the trenches 112 are formed. The trenches 112 are filled with an insulating material (not shown). In some embodiments, the insulating material includes silicon oxide, silicon nitride, silicon oxynitride, a spin-on dielectric material, or a low-k dielectric material. The insulating material is formed by high-density-plasma chemical vapor deposition (HDP-CVD), sub-atmospheric CVD (SACVD) or by spin-on. Optionally, a chemical mechanical polish process is performed to remove the projected insulating material and the remained mask layer 108 (referring to FIG. 2B). Afterwards, the insulating material filled in the trenches 112 between the fins 116 is partially removed by an etching process. In one embodiment, the etching process is performed by using a wet etching process with hydrofluoric acid (HF). In another embodiment, the etching process is performed by using a dry etching process. The insulating material remained within the trenches 112 becomes insulators 114 with top surfaces 114a lower than the top surfaces 116a of the fins 116. Upper portions 117 of the fins 116 protrude from the top surfaces 114a of the insulators 114.