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FinFET device and methods of forming the same

專利號(hào)
US10868183B2
公開日期
2020-12-15
申請人
Taiwan Semiconductor Manufacturing Company, Ltd.(TW Hsinchu)
發(fā)明人
Shahaji B. More; Shih-Chieh Chang; Cheng-Han Lee
IPC分類
H01L29/78; H01L29/66; H01L29/10; H01L29/08; H01L27/092; H01L29/423; H01L21/768; H01L21/8238; H01L21/225; H01L29/161
技術(shù)領(lǐng)域
germanium,dopant,fin,in,region,finfet,layer,epitaxial,segment,silicon
地域: Hsinchu

摘要

A semiconductor device includes a substrate; a fin protruding above the substrate, the fin including a compound semiconductor material that includes a semiconductor material and a first dopant, the first dopant having a different lattice constant than the semiconductor material, where a concentration of the first dopant in the fin changes along a first direction from an upper surface of the fin toward the substrate; a gate structure over the fin; a channel region in the fin and directly under the gate structure; and source/drain regions on opposing sides of the gate structure, the source/drain regions including a second dopant, where a concentration of the second dopant at a first location within the channel region is higher than that at a second location within the channel region, where the concentration of the first dopant at the first location is lower than that at the second location.

說明書

In some embodiments, in the epitaxy process to form the silicon germanium layer 53, the process condition(s) is tuned such that the concentration of germanium in the silicon germanium layer 53 is non-uniform. In other words, the concentration of germanium at a first location within the silicon germanium layer 53 is different from the concentration of germanium at a second location within the silicon germanium layer 53. The non-uniform concentration of germanium is used to compensate for a non-uniform concentration of dopant (e.g., boron) diffused into the channel region from the source/drain region of the p-type device, thereby resulting in a substantially uniform threshold voltage for the p-type device formed, details of which are discussed hereinafter with reference to, e.g., FIGS. 6-10, 24A, 24B, 25A, 25B, and 25C.

Next, in FIG. 5, fins 58 are formed. The fins 58 are semiconductor strips. In the example of FIG. 5, each of the fins 58 in the region 50C includes three layers, e.g., a bottom layer formed of the material of the substrate 50/50P, a middle layer formed of the material of the epitaxial material 52 (e.g., an epitaxial silicon layer), and an upper layer formed of the material of the silicon germanium layer 53. As illustrated in FIG. 5, each of the fins 58 in the region 50B includes two layers, e.g., a bottom layer formed of the material of the substrate 50/50N, and an upper layer formed of the material of the epitaxial material 52 (e.g., an epitaxial silicon layer). In some embodiments, the fins 58 are formed by etching trenches in the substrate 50 and the epitaxial materials (e.g., 52, 53).

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