FIGS. 6-10 illustrate cross-sectional views of various embodiments of the silicon germanium layer 53 in the channel region of the fin 58 (e.g., in the region 50C) of the FinFET device 100 of FIG. 5, in accordance with various embodiments. To illustrate the relative locations, the epitaxial material 52 underlying the silicon germanium layer 53 is also illustrated in FIGS. 6-10. In addition, a capping layer 55 (e.g., a silicon capping layer) over the silicon germanium layer 53 is illustrated in phantom, which capping layer 55 may be formed in subsequent processing (see FIG. 13 and the discussion therein). In FIGS. 6-10, unless otherwise stated, similar numerals refer to the same or similar element that is formed by a same or similar method, thus details may not be repeated.
