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FinFET device and methods of forming the same

專利號(hào)
US10868183B2
公開日期
2020-12-15
申請(qǐng)人
Taiwan Semiconductor Manufacturing Company, Ltd.(TW Hsinchu)
發(fā)明人
Shahaji B. More; Shih-Chieh Chang; Cheng-Han Lee
IPC分類
H01L29/78; H01L29/66; H01L29/10; H01L29/08; H01L27/092; H01L29/423; H01L21/768; H01L21/8238; H01L21/225; H01L29/161
技術(shù)領(lǐng)域
germanium,dopant,fin,in,region,finfet,layer,epitaxial,segment,silicon
地域: Hsinchu

摘要

A semiconductor device includes a substrate; a fin protruding above the substrate, the fin including a compound semiconductor material that includes a semiconductor material and a first dopant, the first dopant having a different lattice constant than the semiconductor material, where a concentration of the first dopant in the fin changes along a first direction from an upper surface of the fin toward the substrate; a gate structure over the fin; a channel region in the fin and directly under the gate structure; and source/drain regions on opposing sides of the gate structure, the source/drain regions including a second dopant, where a concentration of the second dopant at a first location within the channel region is higher than that at a second location within the channel region, where the concentration of the first dopant at the first location is lower than that at the second location.

說明書

Processing continues after the fins 58 are formed in FIG. 5. Referring now to FIG. 11, an insulation material 54 is formed over the substrate 50 and between neighboring fins 58. The insulation material 54 may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the insulation material 54 is silicon oxide formed by a FCVD process. An anneal process may be performed once the insulation material is formed. In an embodiment, the insulation material 54 is formed such that excess insulation material 54 covers the fins 58.

Next, in FIG. 12, a planarization process is applied to the insulation material 54. In some embodiments, the planarization process includes a chemical mechanical polish (CMP), an etch back process, combinations thereof, or the like. The planarization process exposes the fins 58. Top surfaces of the fins 58 and the insulation material 54 are level after the planarization process is complete.

權(quán)利要求

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