FIGS. 15A through 23B illustrate various additional steps in the manufacturing of the FinFET device 100. Although FIGS. 15A through 23B illustrate features in the region 50C, processing in the region 50B may be similar to that in the region 50C. Differences in the structures of the region 50B and the region 50C are described in the text accompanying each figure.

In FIGS. 15A and 15B, the mask layer 64 may be patterned using suitable photolithography and etching techniques to form masks 74. The pattern of the masks 74 then may be transferred to the dummy gate layer 62 by suitable etching technique to form dummy gates 72. The dummy gates 72 cover respective channel regions of the fins 58. The pattern of the masks 74 may be used to physically separate each of the dummy gates 72 from adjacent dummy gates. The dummy gates 72 may also have a lengthwise direction substantially perpendicular to the lengthwise direction of respective fins 58. Respective mask 74, dummy gate 72, and the dummy dielectric layer 60 underlying the dummy gate 72 may be collectively referred to as a dummy gate structure 75.

Further in FIGS. 15A and 15B, gate seal spacers 80 are formed on exposed surfaces of the dummy gates 72, the masks 74, and/or the fins 58. A thermal oxidation or a deposition followed by an anisotropic etch may form the gate seal spacers 80.