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FinFET device and methods of forming the same

專(zhuān)利號(hào)
US10868183B2
公開(kāi)日期
2020-12-15
申請(qǐng)人
Taiwan Semiconductor Manufacturing Company, Ltd.(TW Hsinchu)
發(fā)明人
Shahaji B. More; Shih-Chieh Chang; Cheng-Han Lee
IPC分類(lèi)
H01L29/78; H01L29/66; H01L29/10; H01L29/08; H01L27/092; H01L29/423; H01L21/768; H01L21/8238; H01L21/225; H01L29/161
技術(shù)領(lǐng)域
germanium,dopant,fin,in,region,finfet,layer,epitaxial,segment,silicon
地域: Hsinchu

摘要

A semiconductor device includes a substrate; a fin protruding above the substrate, the fin including a compound semiconductor material that includes a semiconductor material and a first dopant, the first dopant having a different lattice constant than the semiconductor material, where a concentration of the first dopant in the fin changes along a first direction from an upper surface of the fin toward the substrate; a gate structure over the fin; a channel region in the fin and directly under the gate structure; and source/drain regions on opposing sides of the gate structure, the source/drain regions including a second dopant, where a concentration of the second dopant at a first location within the channel region is higher than that at a second location within the channel region, where the concentration of the first dopant at the first location is lower than that at the second location.

說(shuō)明書(shū)

FIG. 25A illustrates the simulated threshold voltage Vt of a FinFET device with dopant diffusion. The FinFET device of FIG. 25A does not counteract the effect of the dopant diffusion with a non-uniform germanium concentration in the channel region. In FIG. 25A, the y-axis illustrates the threshold voltage, and the x-axis illustrates the vertical distance (e.g., depth) between the top surface of the fin and the location in the channel region being measured. As illustrated in FIG. 25A, the FinFET device has a non-uniform threshold voltage.

FIG. 25B illustrates the germanium concentration in the channel region of an embodiment FinFET device. The germanium concentration is designed to counteract the effect of the diffused dopant (see FIG. 25A) in the channel region. FIG. 25C illustrates the simulated threshold voltage of the embodiment FinFET device, which shows a uniform threshold voltage.

Referring back to FIGS. 17C and 17D, as a result of the epitaxy processes used to form the epitaxial source/drain regions 82 in the region 50B and the region 50C, upper surfaces of the epitaxial source/drain regions have facets which expand laterally outward beyond sidewalls of the fins 58. In some embodiments, these facets cause adjacent source/drain regions 82 of a same FinFET device to merge as illustrated by FIG. 17C. In other embodiments, adjacent source/drain regions 82 remain separated after the epitaxy process is completed as illustrated by FIG. 17D.

權(quán)利要求

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