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Semiconductor chip

專利號
US10868192B2
公開日期
2020-12-15
申請人
SOCIONEXT INC.（JP Kanagawa）
發(fā)明人
Hiroyuki Shimbo
IPC分類
H01L29/00; H01L29/786; H01L21/8238; H01L27/092; H01L27/118; H01L29/06; H01L29/775; H01L27/088; H01L29/417; H01L29/423; H01L21/8234; H01L27/02; H01L27/12
技術(shù)領(lǐng)域
nanowire,nanowires,pitch,fet,pads,in,direction,cell,fets,gate
地域： Kanagawa

摘要

Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire FET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.

說明書

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation of International Application No. PCT/JP2017/25300 filed on Jul. 11, 2017, which claims priority to Japanese Patent Application No. 2016-150960 filed on Aug. 1, 2016. The entire disclosures of these applications are incorporated by reference herein.

BACKGROUND

The present disclosure relates to a semiconductor chip including a standard cell including a nanowire field effect transistor (FET).

A standard cell design has been known as a method of forming a semiconductor integrated circuit on a semiconductor substrate. The standard cell design refers to a method of designing a large-scale integrated circuit (LSI) chip by providing in advance, as standard cells, unit logic elements having particular logical functions (for example, an inverter, a latch, a flip-flop, and a full adder), laying out those standard cells on a semiconductor substrate, and connecting those standard cells together through an interconnect.

Reducing a gate length (scaling) of transistors that are a basic element of the LSI have achieved more integrated transistors, reduced an operating voltage, and improved an operating rate. However, recently, off-current has been increased due to excessive scaling, and power has been consumed more and more due to the increase in off-current, which are problems. In order to solve such problems, three-dimensional transistors having a three-dimensional structure that is changed from a conventional two-dimensional structure have been actively researched. As one technique, nanowire FETs draw attention.

權(quán)利要求

1
What is claimed is:1. A semiconductor chip, comprising:a first block including a standard cell having a nanowire field effect transistor (FET); anda second block including a nanowire FET,wherein the nanowire FETs included in the first and second blocks each include:a nanowire extending in a first direction, the nanowire being a single nanowire or including a plurality of parallelly arranged nanowires;a pair of pads that are arranged at both ends of the nanowire in the first direction, each have a lower surface below a lower surface of the nanowire, and are each connected to the nanowire; anda gate electrode that extends in a second direction perpendicular to the first direction, and surrounds a periphery of the nanowire within a predetermined range of the nanowire in the first direction,in the first and second blocks,the nanowires have an arrangement pitch in the second direction of an integer multiple of a predetermined first pitch, andthe pads have an arrangement pitch in the first direction of an integer multiple of a predetermined second pitch.2. The semiconductor chip of claim 1, whereinin at least one of the nanowire FETs included in the first and second blocks, the nanowires are arranged in a third direction perpendicular to the first direction and the second direction, andin the first and second blocks, the nanowires have an arrangement pitch in the third direction of an integer multiple of a predetermined nanowire stack pitch.3. The semiconductor chip of claim 1, whereinin the first and second blocks, a gate line constituting the gate electrode and a dummy gate line have an arrangement pitch in the first direction of an integer multiple of the second pitch.4. The semiconductor chip of claim 1, whereinthe standard cell has a size in the second direction of an integer multiple of the first pitch.5. A semiconductor chip, comprising:a first block including a standard cell having a nanowire field effect transistor (FET); anda second block including a nanowire FET,wherein the nanowire FETs included in the first and second blocks each include:a nanowire extending in a first direction, the nanowire being a single nanowire or including a plurality of parallelly arranged nanowires;a pair of pads that are respectively arranged at both ends of the nanowire in the first direction, each have a lower surface below a lower surface of the nanowire, and are each connected to the nanowire; anda gate electrode that extends in a second direction perpendicular to the first direction, and surrounds a periphery of the nanowire within a predetermined range of the nanowire in the first direction,in at least one of the nanowire FETs included in the first and second blocks, the nanowires are arranged in a third direction perpendicular to the first direction and the second direction,in the first and second blocks, the nanowires have an arrangement pitch in the second direction of an integer multiple of a predetermined first pitch and have an arrangement pitch in the third direction of an integer multiple of a predetermined nanowire stack pitch, andin the first and second blocks, a gate line constituting the gate electrode and a dummy gate line have an arrangement pitch in the first direction of an integer multiple of the second pitch.6. The semiconductor chip of claim 5, whereinin the first and second blocks, the pads have an arrangement pitch in the first direction of an integer multiple of a predetermined second pitch.7. The semiconductor chip of claim 5, whereinthe standard cell has a size in the second direction of an integer multiple of the first pitch.
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