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Semiconductor chip

專利號
US10868192B2
公開日期
2020-12-15
申請人
SOCIONEXT INC.(JP Kanagawa)
發(fā)明人
Hiroyuki Shimbo
IPC分類
H01L29/00; H01L29/786; H01L21/8238; H01L27/092; H01L27/118; H01L29/06; H01L29/775; H01L27/088; H01L29/417; H01L29/423; H01L21/8234; H01L27/02; H01L27/12
技術(shù)領(lǐng)域
nanowire,nanowires,pitch,fet,pads,in,direction,cell,fets,gate
地域: Kanagawa

摘要

Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire FET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.

說明書

The memory block 300 includes memory cells 310, and achieves memory functions such as a static random access memory (SRAM) and a dynamic random access memory (DRAM). The memory cells 310 constitute a memory cell array. The memory block 300 includes peripheral circuits such as a sense amplifier and a decoder in addition to the memory cells 310. The analog block 400 includes analog cells 410, and achieves analog functions such as a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), and a phase-locked loop (PLL). The analog block 400 may include an analog circuit and a digital circuit. The IO block 500 includes IO unit cells 510, and receives and delivers signals from and to the outside of the semiconductor chip 1. The IO block 500 includes circuits such as a level shifter, an electro-static discharge (ESD) circuit, and an input-output buffer.

權(quán)利要求

1
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