FIG. 2 is a plan view of a layout configuration example of a standard cell having nanowire FETs. FIG. 2 also illustrates local interconnects and metal interconnects. The standard cell shown in FIG. 2 and including the nanowire FETs constitutes an inverter having an input A and an output Y. A p-type nanowire FET P1 is provided in a p-type transistor area PA, and an n-type nanowire FET N1 is provided in an n-type transistor area NA. The nanowire FET P1 includes a group of a plurality of parallelly arranged nanowires 11 extending in the X direction, and the nanowire FET N1 includes a group of a plurality of parallelly arranged nanowires 12 extending in the X direction. Here, the groups of nanowires 11, 12 each include nanowires arranged in four rows in the Y direction, and each include eight nanowires in total if they are assumed to include nanowires arranged in two rows in the vertical direction, i.e., the direction perpendicular to the substrate. Each of the nanowires 11, 12 has a cylindrical shape, extends horizontally above the substrate, i.e., extends parallel to the substrate, and is comprised of, e.g., silicon. Pairs of pads 21 and 22 each connected to an associated one of the nanowires 11 and pairs of pads 23 and 24 each connected to an associated one of the nanowires 12 are provided. P-type impurities are introduced into at least portions of the pads 21, 22 connected to the nanowires 11 and serving as source/drain regions of the nanowire FET P1. N-type impurities are introduced into at least portions of the pads 23, 24 connected to the nanowires 12 and serving as source/drain regions of the nanowire FET N1.