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Semiconductor chip

專利號
US10868192B2
公開日期
2020-12-15
申請人
SOCIONEXT INC.（JP Kanagawa）
發(fā)明人
Hiroyuki Shimbo
IPC分類
H01L29/00; H01L29/786; H01L21/8238; H01L27/092; H01L27/118; H01L29/06; H01L29/775; H01L27/088; H01L29/417; H01L29/423; H01L21/8234; H01L27/02; H01L27/12
技術(shù)領(lǐng)域
nanowire,nanowires,pitch,fet,pads,in,direction,cell,fets,gate
地域： Kanagawa

摘要

Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire FET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.

說明書

Here, the groups of the pads 21, 22, 23, 24 each include four pads separately arranged in the Y direction. The pads 21, 22 are each connected to an associated one of the four nanowires 11 arranged in the Y direction. The pads 23, 24 are each connected to an associated one of the four nanowires 12 arranged in the Y direction.

The standard cell of FIG. 2 is provided with a gate line 31 extending linearly in the Y direction. The gate line 31 is comprised of a gate electrode 31p of the nanowire FET P1 and a gate electrode 31n of the nanowire FET N1 which are integrally formed with each other, and surrounds peripheries of the nanowires 11, 12 within predetermined ranges of the nanowires 11, 12 in the X direction. Lateral sides of a cell frame CF of the standard cell of FIG. 2 are respectively provided with dummy gate lines 33a and 33b extending in the Y direction.

權(quán)利要求

1
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