The metallic interconnects 41a to 41d are each connected to an associated one or ones of the pads 21, 22, 23, 24 and the gate line 31 through associated ones of the local interconnects 45a, 45b, 45c, 45d, and 45e and contacts 43. Alternatively, the metallic interconnects may be connected to the pads and the gate line only through the local interconnects, not through the contacts, or may be connected to the pads and the gate line only through the contacts, not through the local interconnects.

FIG. 3 is a schematic cross-sectional view taken along line A-A of the semiconductor chip of FIG. 1, and illustrates a cross-sectional configuration of the low-height standard cell block 100 taken along the X direction. In FIG. 3, the reference numeral 111 indicates nanowires, 112 indicates a pad, 113 indicates a gate line, and 114 indicates a dummy gate line. In the configuration of FIG. 3, the nanowires 111 are stacked in two tiers at the nanowire stack pitch SP in a Z direction (the direction perpendicular to the substrate surface (an XY plane)). Consequently, in a transistor T1, a group of the nanowires 111 extending in the X direction includes nanowires arranged in three rows in the Y direction, nanowires arranged in two rows in the Z direction, and thus includes six (=3×2) nanowires 111 in total.