Here, for example, the low-height standard cell 110 has a cell width (a size in the X direction) that is double the pitch P3, and has a size in the Y direction, i.e., a cell height, that is eight times the pitch P1. The high-height standard cell 210, the memory cell 310, the analog cell 410, and the IO unit cell 510 also have a cell width of an integer multiple of the pitch P3 and have a cell height of an integer multiple of the pitch P1. The low-height standard cell 110 is designed in advance such that, when its contour is aligned with the grid lines L1 and L3, the nanowires extending in the X direction are positioned on the grid lines L1, and the gates extending in the Y direction are positioned on the grid lines L3. The pads are arranged at positions deviated by a half pitch (=P3/2) from the gates in the X direction. The high-height standard cell 210, the memory cell 310, the analog cell 410, and the IO unit cell 510 are also designed similarly. Consequently, a designer who performs layout design aligns the contour of each cell with associated ones of the grid lines L1 and L3 and can thereby easily design the layout configuration as in FIG. 1.