Here, the semiconductor chip 1 of FIG. 1 includes, e.g., the low-height standard cell block 100 including the low-height standard cells 110 having the nanowire FETs as a first block and the analog block 400 including the nanowire FETs as a second block. In the low-height standard cell block 100 and the analog block 400, the nanowires have an arrangement pitch in the Y direction of an integer multiple of the pitch P1, and the pads have an arrangement pitch in the X direction of an integer multiple of the pitch P2. This configuration improves the regularity of arrangement of the nanowires and the pads of the semiconductor chip 1. Consequently, the semiconductor chip 1 is easily manufactured, and a reduction in process-induced variations and improvement in yield can be achieved.

As shown in FIGS. 3 and 4, in the low-height standard cell block 100 and the analog block 400, the nanowires have an arrangement pitch in the Z direction of an integer multiple of the nanowire stack pitch SP. This configuration improves the regularity of arrangement of the nanowires of the semiconductor chip 1. Consequently, the semiconductor chip 1 is easily manufactured, and a reduction in process-induced variations and improvement in yield can be achieved.