A first aspect of the present disclosure is directed to a semiconductor chip including a first block including a standard cell having a nanowire field effect transistor (FET) and a second block including a nanowire FET. The nanowire FETs included in the first and second blocks each include a nanowire extending in a first direction, the nanowire being a single nanowire or including a plurality of parallelly arranged nanowires; a pair of pads that are arranged at both ends of the nanowire in the first direction, each have a lower surface below a lower surface of the nanowire, and are each connected to the nanowire; and a gate electrode that extends in a second direction perpendicular to the first direction, and surrounds a periphery of the nanowire within a predetermined range of the nanowire in the first direction. In the first and second blocks, the nanowires have an arrangement pitch in the second direction of an integer multiple of a predetermined first pitch, and the pads have an arrangement pitch in the first direction of an integer multiple of a predetermined second pitch.

According to this aspect, the semiconductor chip includes the first block including the standard cell having the nanowire FET and the second block including the nanowire FET. In the first and second blocks, the nanowires extending in the first direction have an arrangement pitch in the second direction, i.e., a direction in which the gate electrode extends, of an integer multiple of the predetermined first pitch, and the pads have an arrangement pitch in the first direction of an integer multiple of the predetermined second pitch. This configuration improves the regularity of arrangement of the nanowires and the pads of the semiconductor chip. Consequently, the semiconductor chip is easily manufactured, and a reduction in process-induced variations and improvement in yield can be achieved.