FIG. 1 is a schematic plan view of a layout configuration example of a semiconductor chip according to an embodiment. In FIG. 1, the lateral direction on the paper is an X direction (corresponding to a first direction), and the longitudinal direction on the paper is a Y direction (corresponding to a second direction). FIG. 1 illustrates grid lines L1 extending in the X direction and arranged in parallel at a pitch P1 (corresponding to a first pitch) and grid lines L2 extending in the Y direction and arranged in parallel at a pitch P2 (corresponding to a second pitch). However, in an actual semiconductor chip, the grid lines L1 and L2 are invisible. In FIG. 1, nanowires 111, 411 of nanowire FETs T1 and T2 extend in the X direction, and are aligned with the associated grid lines L1. Nanowires of other nanowire FETs also similarly extend in the X direction, and are aligned with the associated grid lines L1. Pads 112, 412 of the nanowire FETs T1 and T2 are spaced apart from one another in the Y direction, and are arranged on the associated grid lines L2. Pads of the other nanowire FETs are also similarly spaced apart from one another in the Y direction, and are arranged on the associated grid lines L2. FIG. 1 does not illustrate local interconnects, vias, metal interconnects, and other components.