Structure of memory device and fabrication method thereof
地域：
Hsinchu
摘要
A structure of a memory device and a fabrication method thereof are provided. The structure of the memory device includes a tunneling layer disposed on a substrate. A first oxide/nitride/oxide (ONO) layer is disposed on the substrate abutting to the tunneling layer. A floating gate is disposed on the tunneling layer, wherein a side portion of the floating gate is also disposed on the first ONO layer. A second ONO layer is disposed on the floating gate. A control gate is disposed on the second ONO layer. An isolation layer is disposed on first sidewalls of the floating gate and sidewalls of the control gate. An erase gate is disposed on the first ONO layer, wherein the erase gate is isolated from the floating gate and the control gate by the isolation layer.
說明書
This application claims the priority benefit of Chinese patent application serial no. 201910418713.2, filed on May 20, 2019. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
The present invention relates to a semiconductor fabrication technology, and more particularly to a structure of a memory device and a fabrication method thereof.
A non-volatile memory is almost a necessity in digital electronic products. Digital electronic products such as computers, mobile phones, cameras, and video recorders are also indispensable products in daily life. Therefore, the non-volatile memory is generally required.
The non-volatile memory is, for example, a flash memory including a control gate and a floating gate. Since the data stored in the memory is frequently changed according to actual operations, in addition to the operations of writing and reading, the operation of erasing data is often performed. Therefore, the efficiency of erasing data also affects the overall performance of the memory.
The structure of the flash memory is also continuing to be developed in order to improve the overall performance of the memory.
權(quán)利要求
What is claimed is:1. A structure of a memory device, comprising:a tunneling layer, disposed on a substrate; a first oxide/nitride/oxide (ONO) layer, disposed on the substrate abutting to the tunneling layer; a floating gate, disposed on the tunneling layer, wherein a side portion of the floating gate is also disposed on the first ONO layer; a second ONO layer, disposed on the floating gate; a control gate, disposed on the second ONO layer; an isolation layer, disposed on first sidewalls of the floating gate and sidewalls of the control gate; and an erase gate, disposed on the first ONO layer, wherein the erase gate is isolated from the floating gate and the control gate by the isolation layer. 2. The structure of the memory device according to claim 1 , further comprising a vertical dielectric layer on second sidewalls of the side portion of the floating gate, wherein the second sidewalls abut to a shallow trench isolation structure and are merged with the first ONO layer. 3. The structure of the memory device according to claim 2 , wherein the vertical dielectric layer occupies a space to reduce a width of the floating gate. 4. The structure of the memory device according to claim 2 , wherein the vertical dielectric layer comprises an oxide layer and a nitride layer stacked on the second sidewalls. 5. The structure of the memory device according to claim 1 , wherein the isolation layer comprises a first portion disposed on the first sidewalls of the floating gate and a second portion disposed on the sidewalls of the control gate. 6. The structure of the memory device according to claim 5 , wherein the first portion of the isolation layer is an oxide layer, and the second portion of the isolation layer is a third ONO layer. 7. The structure of the memory device according to claim 1 , wherein the control gate does not completely cover over the side portion of the floating gate. 8. The structure of the memory device according to claim 7 , wherein the erase gate comprises a protruding portion at a top region, covering over the side portion of the floating gate and isolated by a portion of the isolation layer. 9. The structure of the memory device according to claim 1 , wherein the substrate comprises:active lines extending in a first direction; and shallow trench isolation lines to isolate the active lines, wherein the control gate is a control gate line and the erase gate is an erase gate line, and the control gate line and the erase gate line extend in a second direction perpendicular to the first direction. 10. The structure of the memory device according to claim 1 , wherein the substrate comprises a P-type well region and an N-type well region in the P-type well region, wherein the floating gate covers over the P-type well region and the N-type well region, and the erase gate covers over the N-type well region. 11. A method of fabricating a memory device, comprising:forming a tunneling layer on a substrate; forming a first oxide/nitride/oxide (ONO) layer on the substrate abutting to the tunneling layer; forming a floating gate on the tunneling layer, wherein a side portion of the floating gate is also disposed on the first ONO layer; forming a second ONO layer on the floating gate; forming a control gate on the second ONO layer; forming an isolation layer on first sidewalls of the floating gate and sidewalls of the control gate; and forming an erase gate on the first ONO layer, wherein the erase gate is isolated from the floating gate and the control gate by the isolation layer. 12. The method of fabricating the memory device according to claim 11 , further comprising:forming a vertical dielectric layer on second sidewalls of the side portion of the floating gate, wherein the second sidewalls abut to a shallow trench isolation structure and are merged with the first ONO layer. 13. The method of fabricating the memory device according to claim 12 , wherein the vertical dielectric layer occupies a space to reduce a width of the floating gate. 14. The method of fabricating the memory device according to claim 12 , wherein the vertical dielectric layer comprises an oxide layer and a nitride layer stacked on the second sidewalls. 15. The method of fabricating the memory device according to claim 11 , wherein the formed isolation layer comprises a first portion disposed on the first sidewalls of the floating gate and a second portion disposed on the sidewalls of the control gate. 16. The method of fabricating the memory device according to claim 15 , wherein the first portion of the isolation layer is an oxide layer, and the second portion of the isolation layer is a third ONO layer. 17. The method of fabricating the memory device according to claim 11 , wherein the control gate does not completely cover over the side portion of the floating gate. 18. The method of fabricating memory device according to claim 17 , wherein the erase gate comprises a protruding portion at a top region, covering over the side portion of the floating gate and isolated by a portion of the isolation layer. 19. The method of fabricating the memory device according to claim 11 , wherein the formed substrate comprises:active lines extending in a first direction; and shallow trench isolation lines to isolate the active lines, wherein the control gate is a control gate line and the erase gate is an erase gate line, and the control gate line and the erase gate line extend in a second direction perpendicular to the first direction. 20. The method of fabricating the memory device according to claim 11 , wherein the substrate comprises a P-type well region and an N-type well region in the P-type well region, wherein the floating gate covers over the P-type well region and the N-type well region, and the erase gate covers over the N-type well region.
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