FIG. 4 is a drawing, schematically illustrating a top view of a floating gate of a memory device in accordance with one embodiment of the present invention. According to FIG. 4, in one embodiment, the floating gate 112 is substantially rectangular or square in geometry as viewed from above. The sidewalls 112B of the floating gate 112 are protected by an isolation layer 120. However, since the ONO layer 200 also extends to the side portion of the floating gate 112, in one embodiment, the other pair of sidewalls 112A of the floating gate 112 are also covered, for example, by the ONO layer 200. In one embodiment, as shown in FIG. 5, which will be described later, a dielectric material covering the sidewalls 112A of the floating gate 112 may generally be a vertical dielectric layer 202. Since the ONO layer 200 occupies the space, the width of the subsequently formed floating gate 112 at the side portion is reduced. Thus, the area between the floating gate 112 and the erase gate 110 is reduced, and the capacitor Ceg-fg generated by the relative has a small capacitance value. After the research of the present invention, the present invention finds that the capacitor Ceg-fg with a smaller capacitance value is advantageous for the erasing operation of the memory device. In addition, since the ONO layer 200 also extends below the floating gate 112, the capacitance value of the capacitor Cfg-sub is also increased, which is also advantageous for the erasing operation of the memory device. Embodiments are provided below to describe the generation mechanism of the capacitor in more detail.
