FIG. 6 is a drawing, schematically illustrating a cross-sectional view of the memory device taken along the cutting line I-I′ of FIG. 2 in accordance with one embodiment of the present invention. According to FIG. 6, the structure of the memory device 90 is the same as the cross-sectional structure of the end face of FIG. 3. In one embodiment, as described above, the sidewall of the mask layer 124 may be a general oxide layer, and does not need to extend from the isolation layer 118, or substantially change the formation of the ONO layer 200 and the vertical dielectric layer 202. The sidewalls 112B of the side portion of the floating gate 112 are isolated by the isolation layer 120 from the lower portion of the erase gate 110.

In the region 300 indicated, the ONO layer 200 produces a capacitance effect between the floating gate 112 and the substrate 100.

FIG. 7 is a drawing, schematically illustrating a partial enlarged view of a memory device in accordance with one embodiment of the present invention. FIG. 8 is a drawing, schematically illustrating a schematic view showing the capacitive effect of the memory device between the floating gate and the substrate in FIG. 7 in accordance with one embodiment of the present invention.