The present invention provides a structure of a memory device and a fabrication method thereof. The memory device is a structure based on a structure including a control gate and a floating gate, which can reduce the capacitance value between the floating gate and an erase gate and increase the capacitance value between the floating gate and a substrate, thereby improving the efficiency of erasing data.

In one embodiment, the present invention provides a structure of a memory device, including a tunneling layer disposed on a substrate. A first oxide-nitride-oxide (ONO) layer is disposed on the substrate abutting to the tunneling layer. A floating gate is disposed on the tunneling layer, wherein a side portion of the floating gate is also disposed on the first ONO layer. A second ONO layer is disposed on the floating gate. A control gate is disposed on the second ONO layer. An isolation layer is disposed on first sidewalls of the floating gate and sidewalls of the control gate. An erase gate is disposed on the first ONO layer, wherein the erase gate is isolated from the floating gate and the control gate by the isolation layer.

In one embodiment, the structure of the memory device further includes a vertical dielectric layer on second sidewalls of the side portion of the floating gate, wherein the second sidewalls abut to a shallow trench isolation structure and are merged with the first ONO layer.

In one embodiment, for the structure of the memory device, the vertical dielectric layer occupies a space to reduce a width of the floating gate.

In one embodiment, for the structure of the memory device, the vertical dielectric layer includes an oxide layer and a nitride layer stacked on the second sidewalls.