In one embodiment, for the structure of the memory device, the isolation layer includes a first portion disposed on the first sidewalls of the floating gate and a second portion disposed on the sidewalls of the control gate.

In one embodiment, for the structure of the memory device, the first portion of the isolation layer is an oxide layer, and the second portion of the isolation layer is a third ONO layer.

In one embodiment, for the structure of the memory device, the control gate does not completely cover over the side portion of the floating gate.

In one embodiment, for the structure of the memory device, the erase gate includes a protruding portion at a top region, covering over the side portion of the floating gate and isolated by a portion of the isolation layer.

In one embodiment, for the structure of the memory device, the substrate includes: active lines extending in a first direction; and shallow trench isolation lines to isolate the active lines. The control gate is a control gate line and the erase gate is an erase gate line, and the control gate and the erase gate extend in a second direction perpendicular to the first direction.

In one embodiment, for the structure of the memory device, the substrate includes a P-type well region and an N-type well region in the P-type well region, wherein the floating gate covers over the P-type well region and the N-type well region, and the erase gate covers over the N-type well region.