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LED chips, method of manufacturing the same, and display panels

專利號
US10868217B2
公開日期
2020-12-15
申請人
Kunshan New Flat Panel Display Technology Center Co., Ltd.; Kunshan Go-Visionox Opto-Electronics Co., Ltd.
發(fā)明人
Dong Wei; Rubo Xing; Huimin Liu; Xiaolong Yang; Jiantai Wang
IPC分類
H01L33/38; H01L33/62; H01L23/00; G09G3/32
技術(shù)領(lǐng)域
electrode,extension,layer,contact,led,second,first,concave,spots,soldering
地域: Kunshan

摘要

An LED chip provided by an embodiment includes a first semiconductor layer; an active layer and a second semiconductor layer located sequentially on the first semiconductor layer. A first contact electrode extends through the active layer and the second semiconductor layer and is electrically connected to the first semiconductor layer; a second contact electrode is located on the second semiconductor layer and is electrically connected to the second semiconductor layer; a first extension electrode is located on the first contact electrode and is electrically connected to the first contact electrode, the first extension electrode comprises a plurality of concave spots for soldering; and a second extension electrode is located on the second contact electrode, electrically connected to the second contact electrode and isolated from the first extension electrode, and the second extension electrode includes a plurality of concave spots for soldering.

說明書

In this exemplary embodiment, the first conductive layer 110 is made of metal, such as gold, silver or aluminum. The metal may be reflective, thereby improving the light extraction efficiency of the LED chip.

In an actual process, the first conductive layer 110 may be formed by an evaporation method. In other exemplary embodiments, the first conductive layer 110 may also be formed by a sputtering or electroplating process.

In this exemplary embodiment, the thickness of the first conductive layer 110 is smaller than the thickness of the nanoimprint pattern layer 109, so that a top surface of the first conductive layer 110 on the forming surface A is lower than a top surface of the nanoimprint layer 109 such that the first conductive layer 110 on the forming surface A is isolated from the first conductive layer 110 on the top surface of the nanoimprint pattern layer 109 to facilitate to remove the first conductive layer 110 on the top surface of the nanoimprint pattern layer 109 by removal of the nanoimprint pattern in a subsequent process, and retain the first conductive layer 110 on the forming surface A.

權(quán)利要求

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