Self-aligned encapsulation hard mask to separate physically under-etched MTJ cells to reduce conductive R-deposition
地域：
Hsinchu
摘要
A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure.
說明書
This application relates to the general field of magnetic tunneling junctions (MTJ) and, more particularly, to etching methods for forming MTJ structures.
Fabrication of magnetoresistive random-access memory (MRAM) devices normally involves a sequence of processing steps during which many layers of metals and dielectrics are deposited and then patterned to form a magnetoresistive stack as well as electrodes for electrical connections. To define the magnetic tunnel junctions (MTJ) in each MRAM device, precise patterning steps including photolithography and reactive ion etching (RIE), ion beam etching (IBE) or their combination are usually involved. During RIE, high energy ions remove materials vertically in those areas not masked by photoresist, separating one MTJ cell from another.
However, the high energy ions can also react with the non-removed materials, oxygen, moisture and other chemicals laterally, causing sidewall damage and lowering device performance. To solve this issue, pure physical etching techniques such as Ar RIE or ion beam etching (IBE) have been applied to etch the MTJ stack. However, due to the non-volatile nature, physically etched conductive materials in the MTJ and bottom electrode can form a continuous path across the tunnel barrier, resulting in shorted devices. A new approach to overcome this dilemma is thus needed if one wants to unleash the full potential of this physical etch to pattern the future sub 60 nm MRAM products.
Several references teach multi-step etching methods to form MTJ's, including U.S. Pat. No. 9,793,126 (Dhindsa et al), U.S. Pat. No. 9,722,174 (Nagel et al), and U.S. Pat. No. 8,883,520 (Satoh et al). All of these references are different from the present disclosure.
權(quán)利要求
What is claimed is:1. A method for fabricating a magnetic tunneling junction (MTJ) structure comprising:depositing a MTJ stack on a bottom electrode wherein said MTJ stack comprises at least a pinned layer, a barrier layer on said pinned layer, and a free layer on said barrier layer; depositing a top electrode layer on said MTJ stack; depositing a hard mask on said top electrode layer; first etching said top electrode layer and said hard mask with a first etch process; thereafter second etching said MTJ stack using the hard mask as a mask and stopping said etching at or within said pinned layer with a second etch process different from the first etch process; thereafter depositing an encapsulation layer over partially etched said MTJ stack and said hard mask and etching away said encapsulation layer on horizontal surfaces leaving a self-aligned hard mask on sidewalls of said partially etched MTJ stack; and thereafter third etching remaining said MTJ stack not covered by said hard mask and said self-aligned hard mask to complete said MTJ structure. 2. The method according to claim 1 wherein said top electrode layer comprises Ta, TaN, Ti, TiN, W, Cu, Mg, Ru, Cr, Co, Fe, Ni or their alloys and said hard mask comprises SiO2, SiN, SiON, SiC or SiCN. 3. The method according to claim 1 wherein the first etch process for etching said hard mask and said top electrode includes a fluorine carbon based plasma comprising CF4 or CHF3 alone, or mixed with Ar and N2. 4. The method according to claim 3 wherein the second etch process for etching said second includes a physical reactive ion etching using Ar or Xe gas plasma or ion beam etching. 5. The method according to claim 1 wherein there is no chemical damage to sidewalls of said MTJ stack and wherein any first conductive metal re-deposition after said second etching and second conductive metal re-deposition after said third etching are separated from each other by said self-aligned hard mask. 6. The method according to claim 1 wherein said depositing said encapsulation layer comprises depositing a dielectric layer comprising SiN, SiC, SiCN, carbon, or TaC or a metal oxide layer comprising Al2O3 MgO in-situ or ex-situ by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALO) to a thickness of 5-30 nm. 7. The method according to claim 1 wherein a pattern size of said pinned layer is controlled by tuning a thickness of said self-aligned hard mask. 8. The method according to claim 1 wherein a pattern size of said pinned layer is larger than a pattern size of said free layer. 9. A method for fabricating a magnetic tunneling junction (MTJ) structure comprising:depositing a MTJ stack on a bottom electrode wherein said MTJ stack comprises at least a seed layer, a pinned layer on said seed layer, a barrier layer on said pinned layer, and a free layer on said barrier layer; depositing a top electrode layer on said MTJ stack; depositing a hard mask on said top electrode layer; first etching said top electrode layer and said hard mask; thereafter second etching said MTJ stack not covered by said hard mask and stopping said etching at or within said pinned layer or said seed layer; thereafter depositing an encapsulation layer over partially etched said MTJ stack and said hard mask and etching away said encapsulation layer on horizontal surfaces leaving a self-aligned hard mask on sidewalls of said partially etched MTJ stack, including sidewalls of said pinned layer; and thereafter third etching remaining said MTJ stack not covered by said hard mask and said self-aligned hard mask to complete said MTJ structure. 10. The method according to claim 9 wherein a pattern size of said pinned layer is larger than a pattern size of said free layer. 11. The method according to claim 9 wherein said top electrode layer comprises Ta, TaN, Ti, TiN, W, Cu, Mg, Ru, Cr, Co, Fe, Ni or their alloys and said hard mask comprises SiO2, SiN, SiON, SiC or SiCN. 12. The method according to claim 9 wherein said hard mask and said top electrode are etched by a fluorine carbon based plasma comprising CF4 or CHF3 alone, or mixed with Ar and N2, wherein O2 is optionally added to reduce a pattern size of said hard mask, or by physical RIE or IBE, followed by large angle IBE trimming to reduce a pattern size of said hard mask. 13. The method according to claim 9 wherein said second and third etching comprise a physical reactive ion etching using Ar or Xe gas plasma or ion beam etching. 14. The method according to claim 9 wherein there is no chemical damage to sidewalls of said MTJ stack and wherein any first conductive metal re-deposition after said second etching and second conductive metal re-deposition after said third etching are separated from each other by said self-aligned hard mask. 15. The method according to claim 9 wherein said depositing said encapsulation layer comprises depositing a dielectric layer comprising SiN, SiC, SiCN, carbon, or Tac or a metal oxide layer comprising Al2O 3 or MgO in-situ or ex-situ by CVD, PVD, or ALD to a thickness of 5-30 nm. 16. The method according to claim 9 wherein a pattern size of said pinned layer is controlled by tuning a thickness of said self-aligned hard mask. 17. A magnetic tunneling junction (MTJ) structure comprising:separate and non-interacting MTJ cells on a bottom electrode, wherein each said MTJ cell comprises:a seed layer over said bottom electrode, a pinned layer over said seed layer, a barrier layer over said pinned layer, and a free layer over said barrier layer, said seed layer having a top surface facing away from said bottom electrode; sidewall spacers disposed along sidewalls of said pinned layer and extending to a physically contacting said top surface of said seed layer, and a top electrode over said free layer. 18. The structure according to claim 17 wherein said sidewall spacers comprise a dielectric layer comprising SiN, SiC, SiCN, carbon, or TaC or a metal oxide layer comprising Al2O3 or MgO. 19. The structure according to claim 17 wherein a pattern size of said pinned layer or said pinned layer and said seed layer is larger than a pattern size of said free layer. 20. The structure according to claim 17 , wherein the top electrode has a first sidewall surface and an opposing second sidewall surface, andwherein a first portion of said first sidewall surface is free of said sidewall spacers and a second portion of said second sidewall surface is free of said sidewall spacers.
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