A buffer layer 12 such as silicon nitride, silicon oxynitride, or silicon oxide layer may be on the substrate 11. A semiconductor layer 13 may be on the buffer layer 12. The semiconductor layer 13 may include an inorganic semiconductor material such as amorphous silicon or crystalline silicon. In some implementations, the semiconductor layer 13 may include an oxide semiconductor or an organic semiconductor material.

A gate electrode 15 may be on the semiconductor layer 13. A gate insulating layer 14 including an inorganic material, for example, silicon oxynitride, silicon oxide, and/or silicon nitride may be between the gate electrode 15 and the semiconductor layer 13.

The semiconductor layer 13 may include a channel region 13-2 overlapping the gate electrode 15 and a source region 13-1 and a drain region 13-3 located on both sides of the channel region 13-2. The source region 13-1 and the drain region 13-3 may be respectively connected to a source electrode 17-1 and a drain electrode 17-2. The source electrode 17-1 and the drain electrode 17-2 may be on a interlayer insulating layer 16. The interlayer insulating layer 16 may include an inorganic material such as silicon oxynitride, silicon oxide, and/or silicon nitride.

The source electrode 17-1 and the drain electrode 17-2 may be respectively connected to the source region 13-1 and the drain region 13-3 through a contact hole passing through the interlayer insulating layer 16 and the gate insulating layer 14.