FIG. 1 depicts comparators A1, A2, A3, A4 are implemented for each capacitor C1, C2, C3, Cn in order to precisely limit the charging time constant. In turn, each distinct comparator A1, A2, A3, A4 works efficiently for aging capacitors, tolerances, and environmental factors. The output of each of the comparators A1, A2, A3, A4 is provided to a control logic controller (not shown). In one or more embodiments, the output of the comparators A1, A2, A3, A4 is provided to a NOR logic gate A6 to provide feedback to a control logic controller such as a microcontroller to initiate the discharge of the capacitors. In a non-limiting example, all comparators A1, A2, A3, A4 output goes logic LOW then the NOR gate A6 output goes logic HIGH and is provided to the microcontroller. Further, the comparator output will deactivate the current sources I1, I2, I3, I4 once the capacitor reaches a specified voltage level.